PIC16C774-E/L Microchip Technology, PIC16C774-E/L Datasheet - Page 15

• Manufacturer Part Number: PIC16C774-E/L
• Description: IC MCU OTP 4KX14 A/D PWM 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C774-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-PLCC
• For Use With: DVA16XL441 - ADAPTER DEVICE ICE 44PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC16C774E/L

TABLE 2-1
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch-
10Fh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch-
18Fh
Legend:
Note 1:
Address Name
Bank 2
Bank 3
1999 Microchip Technology Inc.
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(1,4)
(4)
(1,4)
(4)
2:
3:
4:
5:
OPTION_REG
INDF
TMR0
PCL
STATUS
FSR
PORTB
PCLATH
INTCON
INDF
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to
the upper byte of the program counter.
Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
These registers can be addressed from any bank.
These registers/bits are not implemented on the 28-pin devices read as '0'.
—
—
—
—
—
—
—
—
—
—
PIC16C77X SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Addressing this location uses contents of FSR to address data memory (not a physical register)
PORTB Data Latch when written: PORTB pins when read
Addressing this location uses contents of FSR to address data memory (not a physical register)
PORTB Data Direction Register
Timer0 module’s register
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
RBPU
Bit 7
IRP
GIE
IRP
GIE
—
—
INTEDG
PEIE
PEIE
Bit 6
RP1
RP1
—
—
T0CS
Bit 5
RP0
T0IE
RP0
T0IE
Advance Information
—
—
Write Buffer for the upper 5 bits of the Program Counter
Write Buffer for the upper 5 bits of the Program Counter
T0SE
INTE
INTE
Bit 4
TO
TO
Bit 3
RBIE
RBIE
PSA
PD
PD
Bit 2
T0IF
T0IF
PS2
Z
Z
INTF
INTF
Bit 1
PS1
DC
DC
PIC16C77X
Bit 0
RBIF
RBIF
PS0
C
C
DS30275A-page 15
Value on:
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
xxxx 11xx
0000 000x
0000 0000
0000 0000
0001 1xxx
xxxx xxxx
0000 000x
1111 1111
1111 1111
---0 0000
---0 0000
POR,
BOR
—
—
—
—
—
—
—
—
—
—
other resets
Value on all
0000 0000
uuuu uuuu
0000 0000
000q quuu
uuuu uuuu
0000 000u
0000 0000
0000 0000
000q quuu
uuuu uuuu
0000 000u
uuuu 11uu
1111 1111
1111 1111
---0 0000
---0 0000
(2)
—
—
—
—
—
—
—
—
—
—