PIC16C774-E/L Microchip Technology, PIC16C774-E/L Datasheet - Page 57

• Manufacturer Part Number: PIC16C774-E/L
• Description: IC MCU OTP 4KX14 A/D PWM 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C774-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-PLCC
• For Use With: DVA16XL441 - ADAPTER DEVICE ICE 44PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC16C774E/L

8.1
The SPI mode allows 8-bits of data to be synchro-
nously transmitted and received simultaneously. All
four modes of SPI are supported. To accomplish com-
munication, typically three pins are used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
Additionally, a fourth pin may be used when in a slave
mode of operation:
• Slave Select (SS)
8.1.1
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master Mode (SCK is the clock output)
• Slave Mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data input sample phase
• Clock edge
• Clock Rate (Master mode only)
• Slave Select Mode (Slave mode only)
Figure 8-4
ule when in SPI mode.
(middle or end of data output time)
(output data on rising/falling edge of SCK)
1999 Microchip Technology Inc.
SPI Mode
OPERATION
shows the block diagram of the MSSP mod-
Advance Information
FIGURE 8-4:
The MSSP consists of a transmit/receive Shift Register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8-bits of data
have been received, that byte is moved to the SSPBUF
register.
(SSPSTAT<0>) and the interrupt flag bit SSPIF
(PIR1<3>) are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit WCOL (SSPCON<7>) will be
set. User software must clear the WCOL bit so that it
can be determined if the following write(s) to the SSP-
BUF register completed successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer
full bit, BF (SSPSTAT<0>), indicates when the SSP-
BUF has been loaded with the received data (transmis-
sion is complete). When the SSPBUF is read, bit BF is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the MSSP Interrupt is used to
SDO
SCK
SDI
SS
Then
Read
SS Control
Select
MSSP BLOCK DIAGRAM
SMP:CKE
(SPI MODE)
Edge
the
Enable
bit0
Select
Edge
SSPBUF reg
Data to TX/RX in SSPSR
Data direction bit
2
SSPM3:SSPM0
SSPSR reg
buffer
PIC16C77X
Clock Select
4
2
full
DS30275A-page 57
Write
Prescaler
4, 16, 64
detect
clock
shift
TMR2 output
data bus
Internal
2
bit
T
OSC
BF