ATMEGA64-16MC Atmel, ATMEGA64-16MC Datasheet - Page 258

• Manufacturer Part Number: ATMEGA64-16MC
• Description: IC AVR MCU 64K 16MHZ COM 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64-16MC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-MLF®, 64-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Boundary-scan
Related Register in
I/O Memory
MCUCSR – MCU
Control and Status
Register
Boundary-scan
Chain
Scanning the Digital
Port Pins
2490Q–AVR–06/10
The MCU Control and Status Register contains control bits for general MCU functions, and pro-
vides information on which reset source caused an MCU Reset.
• Bit 7 – JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this
bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of
the JTAG interface, a timed sequence must be followed when changing this bit: The application
software must write this bit to the desired value twice within four cycles to change its value.
If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to
one. The reason for this is to avoid static current at the TDO pin in the JTAG interface.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Brown-out Reset, or by writing a logic
zero to the flag.
The Boundary-scan Chain has the capability of driving and observing the logic levels on the dig-
ital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
Off-chip connection.
Figure 127
cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn – function, and a
bi-directional pin cell that combines the three signals, Output Control – OCxn, Output Data –
ODxn, and Input Data – IDxn, into only a two-stage Shift Register. The port and pin indexes are
not used in the following description.
The Boundary-scan logic is not included in the figures in this Datasheet.
simple digital Port Pin as described in the section
details from
When no alternate port function is present, the Input Data – ID corresponds to the PINxn Regis-
ter value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output
Control corresponds to the Data Direction – DD Register, and the Pull-up Enable – PUExn – cor-
responds to logic expression PUD · DDxn · PORTxn.
Digital alternate port functions are connected outside the dotted box in
scan chain read the actual pin value. For analog function, there is a direct connection from the
external pin to the analog circuit, and a scan chain is inserted on the interface between the digi-
tal logic and the analog circuitry.
Bit
0x34 (0x54)
Read/Write
Initial Value
shows the Boundary-scan Cell for a bi-directional port pin with pull-up function. The
Figure 127
R/W
JTD
7
0
R
6
–
0
replaces the dashed box in
R
5
–
0
JTRF
R/W
4
WDRF
R/W
3
See Bit Description
“I/O Ports” on page
Figure
BORF
R/W
2
128.
EXTRF
R/W
1
ATmega64(L)
66. The Boundary-scan
PORF
Figure 128
R/W
0
Figure 128
MCUCSR
to make the
shows a
258