ATMEGA64-16MC Atmel, ATMEGA64-16MC Datasheet - Page 94

• Manufacturer Part Number: ATMEGA64-16MC
• Description: IC AVR MCU 64K 16MHZ COM 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64-16MC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-MLF®, 64-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Definitions
Timer/Counter
Clock Sources
2490Q–AVR–06/10
tive when no clock source is selected. The output from the Clock Select logic is referred to as the
timer clock (clk
The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter
value at all times. The result of the compare can be used by the Waveform Generator to gener-
ate a PWM or variable frequency output on the Output Compare pin (OC0).
Compare Unit” on page 95.
(OCF0) which can be used to generate an Output Compare interrupt request.
Many register and bit references in this datasheet are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. However, when using the register or bit
defines in a program, the precise form must be used, that is TCNT0 for accessing
Timer/Counter0 counter value and so on.
The definitions in
Table 51. Definitions
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source clk
bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter
Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see
– Asynchronous Status Register” on page
“Timer/Counter Prescaler” on page
BOTTOM
MAX
TOP
The counter reaches the BOTTOM when it becomes zero (0x00).
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest
value in the count sequence. The TOP value can be assigned to be the
fixed value 0xFF (MAX) or the value stored in the OCR0 Register. The
assignment is dependent on the mode of operation.
T0
).
Table 51
are also used extensively throughout this section.
for details. The Compare Match event will also set the Compare Flag
T0
110.
is by default equal to the MCU clock, clk
107. For details on clock sources and prescaler, see
ATmega64(L)
I/O
. When the AS0
See “Output
“ASSR
94