ATMEGA64-16MC Atmel, ATMEGA64-16MC Datasheet - Page 286

• Manufacturer Part Number: ATMEGA64-16MC
• Description: IC AVR MCU 64K 16MHZ COM 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64-16MC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-MLF®, 64-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Reading the Fuse and
Lock Bits from
Software
Preventing Flash
Corruption
2490Q–AVR–06/10
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruc-
tion is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR,
the value of the Lock bits will be loaded in the destination register. The BLBSET and SPMEN
bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed
within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLB-
SET and SPMEN are cleared, LPM will work as described in the AVR Instruction Set Reference
Manual.
The algorithm for reading the Fuse Low bits is similar to the one described above for reading the
Lock bits. To read the Fuse Low bits, load the Z-pointer with 0x0000 and set the BLBSET and
SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the
BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low bits (FLB) will be
loaded in the destination register as shown below. Refer to
description and mapping of the Fuse Low bits.
Similarly, when reading the Fuse High bits, load 0x0003 in the Z-pointer. When an LPM instruc-
tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR,
the value of the Fuse High bits (FHB) will be loaded in the destination register as shown below.
Refer to
When reading the Extended Fuse bits, load 0x0002 in the Z-pointer. When an LPM instruction is
executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the
value of the Extended Fuse bits (EFB) will be loaded in the destination register as shown below.
Refer to
Fuse and Lock bits that are programmed will be read as zero. Fuse and Lock bits that are unpro-
grammed will be read as one.
During periods of low V
low for the CPU and the Flash to operate properly. These issues are the same as for board level
systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Second,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock
2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
Bit
Rd
Bit
Rd
Bit
Rd
Bit
Rd
bits to prevent any Boot Loader software updates.
This can be done by enabling the internal Brown-out Detector (BOD) if the operating volt-
age matches the detection level. If not, an external low V
Table 118 on page 292
Table 117 on page 291
FHB7
FLB7
7
–
7
7
7
–
FHB6
FLB6
CC,
6
6
6
–
6
–
the Flash program can be corrupted because the supply voltage is too
BLB12
FHB5
FLB5
for detailed description and mapping of the Fuse High bits.
for detailed description and mapping of the Fuse High bits.
5
5
5
5
–
BLB11
FHB4
FLB4
4
4
4
4
–
BLB02
FHB3
FLB3
3
3
3
3
–
BLB01
FHB2
FLB2
2
2
2
2
–
Table 119 on page 292
CC
Reset Protection circuit can
FHB1
FLB1
EFB1
LB2
1
1
1
1
ATmega64(L)
FHB0
FLB0
EFB0
LB1
0
0
0
0
for a detailed
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