AT90CAN128-16AI Atmel, AT90CAN128-16AI Datasheet - Page 307

IC MCU AVR FLASH 128K 64TQFP

AT90CAN128-16AI

Manufacturer Part Number
AT90CAN128-16AI
Description
IC MCU AVR FLASH 128K 64TQFP
Manufacturer
Atmel
Series
AVR® 90CANr
Datasheets

Specifications of AT90CAN128-16AI

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
AT90CAN128-16AI
Manufacturer:
ALTERA
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101
Part Number:
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Manufacturer:
ATMEL
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AT90CAN128-16AI
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10 000
23.6.3
23.6.4
7679H–CAN–08/08
Scanning the RESET Pin
Scanning the Clock Pins
Figure 23-5. Additional Scan Signal for the Two-wire Interface
The RESET pin accepts 3V or 5V active low logic for standard reset operation, and 12V active
high logic for High Voltage Parallel programming. An observe-only cell as shown in
is inserted both for the 3V or 5V reset signal - RSTT, and the 12V reset signal - RSTHV.
Figure 23-6. Observe-only Cell for RESET pin
The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscilla-
tor, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and
Ceramic Resonator.
Figure 23-7
The Enable signal is supported with a general Boundary-scan cell, while the Oscillator/clock out-
put is attached to an observe-only cell. In addition to the main clock, the Timer2 Oscillator is
scanned in the same way. The output from the internal RC Oscillator is not scanned, as this
oscillator does not have external connections.
shows how each oscillator with external connection is supported in the scan chain.
Pxn
From System Pin
Previous
From
Cell
ShiftDR
0
1
ClockDR
D
FF1
Slew-rate limited
Q
AT90CAN32/64/128
Next
Cell
To
SRC
To System Logic
OCxn
ODxn
TWIEN
IDxn
PUExn
Figure 23-6
307

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