AT91FR40161-CI Atmel, AT91FR40161-CI Datasheet - Page 9

• Manufacturer Part Number: AT91FR40161-CI
• Description: IC MCU ARM7 2M FLASH 120-BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91FR40161-CI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 2MB (1M x 16)
• Program Memory Type: FLASH
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 120-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Product Overview
Power Supply
Input/Output
Considerations
Master Clock
Reset
NRST Pin
Watchdog Reset
Emulation Functions
Tri-state Mode
JTAG/ICE Debug
6040B–ATARM–03/04
The AT91FR40161 has a single power supply pin, V
pads and the core. The supported voltage range on V
The AT91FR40161 I/O pads accept voltage levels up to the power supply limit. After
reset, the microcontroller peripheral I/Os are initialized as inputs to provide the user with
maximum flexibility. It is recommended that in any application phase, the inputs to the
microcontroller be held at valid logic levels to minimize the power consumption.
The AT91FR40161 has a fully static design and works on the Master Clock (MCK), pro-
vided on the MCKI pin from an external source.
The Master Clock is also provided as an output of the device on the pin MCKO, which is
multiplexed with a general purpose I/O line. While NRST is active, and after the reset,
the MCKO is valid and outputs an image of the MCK signal. The PIO Controller must be
programmed to use this pin as standard I/O line.
Reset restores the default states of the user interface registers (defined in the user inter-
face of each peripheral), and forces the ARM7TDMI to perform the next instruction fetch
from address zero. Except for the program counter, the ARM7TDMI registers do not
have defined reset states.
NRST is active low-level input. It is asserted asynchronously, but exit from reset is syn-
chronized internally to the MCK. The signal presented on MCKI must be active within
the specification for a minimum of 10 clock cycles up to the rising edge of NRST to
ensure correct operation. The first processor fetch occurs 80 clock cycles after the rising
edge of NRST.
The watchdog can be programmed to generate an internal reset. In this case, the reset
has the same effect as the NRST pin assertion, but the pins BMS and NTRI are not
sampled. Boot Mode and Tri-state Mode are not updated. If the NRST pin is asserted
and the watchdog triggers the internal reset, the NRST pin has priority.
The AT91FR40161 microcontroller provides a tri-state mode, which is used for debug
purposes. This enables the connection of an emulator probe to an application board
without having to desolder the device from the target board. In tri-state mode, all the out-
put pin drivers of the AT91R40807 microcontroller are disabled.
In Tri-state Mode, direct access to the Flash via external pins is provided. This enables
production Flash programming using standard Flash programmers prior to board
mounting.
To enter tri-state mode, the NTRI pin must be held low during the last ten clock cycles
before the rising edge of NRST. For normal operation, the NTRI pin must be held high
during reset by a resistor of up to 400 k .
NTRI is multiplexed with I/O line P21 and USART1 serial data transmit line TXD1.
ARM standard embedded In-circuit Emulation is supported via the JTAG/ICE port. The
pins TDI, TDO, TCK and TMS are dedicated to this debug function and can be con-
nected to a host computer via the external ICE interface. In ICE Debug Mode, the
DD
DD
is 2.7V to 3.6V.
. The V
AT94FR40161
DD
pin supplies the I/O
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