ATMEGA165-16MI Atmel, ATMEGA165-16MI Datasheet - Page 150

• Manufacturer Part Number: ATMEGA165-16MI
• Description: IC AVR MCU 16K 16MHZ 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA165-16MI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Internal Clock Generation –
The Baud Rate Generator
2573G–AVR–07/09
Figure 70. Clock Generation Logic, Block Diagram
Signal description:
Internal clock generation is used for the asynchronous and the synchronous master
modes of operation. The description in this section refers to Figure 70.
The USART Baud Rate Register (UBRR) and the down-counter connected to it function
as a programmable prescaler or baud rate generator. The down-counter, running at sys-
tem clock (f
to zero or when the UBRRL Register is written. A clock is generated each time the coun-
ter reaches zero. This clock is the baud rate generator clock output (= f
The Transmitter divides the baud rate generator clock output by 2, 8 or 16 depending on
mode. The baud rate generator output is used directly by the Receiver’s clock and data
recovery units. However, the recovery units use a state machine that uses 2, 8 or 16
states depending on mode set by the state of the UMSEL, U2X and DDR_XCK bits.
Table 64 contains equations for calculating the baud rate (in bits per second) and for
calculating the UBRR value for each mode of operation using an internally generated
clock source.
txclk
rxclk
xcki
xcko
fosc
DDR_XCK
XCK
Pin
Transmitter clock (Internal Signal).
Receiver base clock (Internal Signal).
Input from XCK pin (internal Signal). Used for synchronous slave operation.
Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
XTAL pin frequency (System Clock).
osc
xcko
xcki
), is loaded with the UBRR value each time the counter has counted down
OSC
Down-Counter
Prescaling
Register
UBRR
Sync
UBRR+1
fosc
Detector
UCPOL
Edge
/2
/4
/2
ATmega165/V
DDR_XCK
U2X
0
1
0
1
osc
/(UBRR+1)).
0
1
1
0
UMSEL
txclk
rxclk
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