ATMEGA165-16MI Atmel, ATMEGA165-16MI Datasheet - Page 53

• Manufacturer Part Number: ATMEGA165-16MI
• Description: IC AVR MCU 16K 16MHZ 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA165-16MI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

External Interrupt Mask
Register – EIMSK
External Interrupt Flag
Register – EIFR
2573G–AVR–07/09
• Bit 7 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will
cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is exe-
cuted from the PCI1 Interrupt Vector. PCINT15..8 pins are enabled individually by the
PCMSK1 Register.
• Bit 6 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause
an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed
from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0
Register.
• Bit 0 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the External Interrupt Control Register A (EICRA) define whether the external
interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity
on the pin will cause an interrupt request even if INT0 is configured as an output. The
corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Inter-
rupt Vector.
• Bit 7 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1
becomes set (one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-
rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
• Bit 6 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0
becomes set (one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-
rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
PCIE1
PCIF1
R/W
R/W
7
0
7
0
PCIE0
PCIF0
R/W
R/W
6
0
6
0
R
R
5
–
0
5
–
0
R
R
4
–
0
4
–
0
R
R
3
–
0
3
–
0
R
R
2
–
0
2
–
0
ATmega165/V
R
R
1
–
0
1
–
0
INTF0
INT0
R/W
R/W
0
0
0
0
EIMSK
EIFR
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