AT89C51SND1C-7HTUL Atmel, AT89C51SND1C-7HTUL Datasheet - Page 10

• Manufacturer Part Number: AT89C51SND1C-7HTUL
• Description: IC MCU 64KB FLASH MEM 81-CBGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND1C-7HTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 81-CBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10
AT8xC51SND1C
Table 11. Keypad Interface Signal Description
Table 12. External Access Signal Description
Notes:
Table 13. System Signal Description
1. For ROM/Flash Dice product versions: pad EA must be connected to VCC.
2. For ROMless Dice product versions: pad EA must be connected to VSS.
Signal
KIN3:0
Signal
EA
Signal
AD7:0
Name
Name
PSEN
Name
A15:8
ALE
RST
TST
ISP
WR
RD
(1)(2)
Type
Type
Type
I/O
I/O
I/O
I/O
O
O
O
I
I
I
I
Description
Keypad Input Lines
Holding one of these pins high or low for 24 oscillator periods triggers a
keypad interrupt.
Description
Address Lines
Upper address lines for the external bus.
Multiplexed higher address and data lines for the IDE interface.
Address/Data Lines
Multiplexed lower address and data lines for the external memory or the
IDE interface.
Address Latch Enable Output
ALE signals the start of an external bus cycle and indicates that valid
address information is available on lines A7:0. An external latch is used
to demultiplex the address from address/data bus.
Program Store Enable Output (AT80C51SND1C Only)
This signal is active low during external code fetch or external code
read (MOVC instruction).
ISP Enable Input (AT89C51SND1C Only)
This signal must be held to GND through a pull-down resistor at the
falling reset to force execution of the internal bootloader.
Read Signal
Read signal asserted during external data memory read operation.
Write Signal
Write signal asserted during external data memory write operation.
External Access Enable (Dice Only)
EA must be externally held low to enable the device to fetch code from
external program memory locations 0000h to FFFFh.
Description
Reset Input
Holding this pin high for 64 oscillator periods while the oscillator is
running resets the device. The Port pins are driven to their reset
conditions when a voltage lower than V
oscillator is running.
This pin has an internal pull-down resistor which allows the device to be
reset by connecting a capacitor between this pin and V
Asserting RST when the chip is in Idle mode or Power-Down mode
returns the chip to normal operation.
Test Input
Test mode entry signal. This pin must be set to V
IL
is applied, whether or not the
DD
.
DD
.
4109L–8051–02/08
Alternate
Alternate
Alternate
Function
Function
Function
P1.3:0
P2.7:0
P0.7:0
P3.7
P3.6
-
-
-
-
-
-