AT89C51SND1C-7HTUL Atmel, AT89C51SND1C-7HTUL Datasheet - Page 52

• Manufacturer Part Number: AT89C51SND1C-7HTUL
• Description: IC MCU 64KB FLASH MEM 81-CBGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND1C-7HTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 81-CBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.5
52
Registers
AT8xC51SND1C
Notes:
Table 60. PCON Register
PCON (S:87h) – Power Configuration Register
Reset Value = 00XX 0000b
–
A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU and
peripherals. Program execution momentarily resumes with the instruction
immediately following the instruction that activated Power-down mode and may
continue for a number of clock cycles before the internal reset algorithm takes
control. Reset initializes the AT8xC51SND1C and vectors the CPU to address
0000h.
1. During the time that execution resumes, the internal RAM cannot be accessed; however, it is
2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal RAM
Number
SMOD1
possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the
instruction immediately following the instruction that activated the Power-down mode should
not write to a Port pin or to the external RAM.
content.
5 - 4
Bit
7
7
6
3
2
1
0
Mnemonic Description
SMOD0
SMOD1
SMOD0
GF1
GF0
IDL
PD
Bit
6
-
Serial Port Mode Bit 1
Set to select double baud rate in mode 1,2 or 3.
Serial Port Mode Bit 0
Set to select FE bit in SCON register.
Clear to select SM0 bit in SCON register.
Reserved
The value read from these bits is indeterminate. Do not set these bits.
General-Purpose Flag 1
One use is to indicate whether an interrupt occurred during normal operation or
during Idle mode.
General-Purpose Flag 0
One use is to indicate whether an interrupt occurred during normal operation or
during Idle mode.
Power-Down Mode Bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Power-down mode.
If IDL and PD are both set, PD takes precedence.
Idle Mode Bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Idle mode.
If IDL and PD are both set, PD takes precedence.
5
-
4
-
GF1
3
GF0
2
PD
1
4109L–8051–02/08
IDL
0