AT89C51SND1C-7HTUL Atmel, AT89C51SND1C-7HTUL Datasheet - Page 102

• Manufacturer Part Number: AT89C51SND1C-7HTUL
• Description: IC MCU 64KB FLASH MEM 81-CBGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND1C-7HTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 81-CBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

102
AT8xC51SND1C
Reset Value = 1000 0000b
Table 97. UEPSTAX Register
UEPSTAX (S:CEh) – USB Endpoint X Status and Control Register (X = EPNUM set in UEPNUM
Number
DIR
1-0
Bit
7
6
5
4
3
2
7
Mnemonic Description
EPTYPE1:
RXOUTB1
NAKOUT
NAKIEN
NAKIN
EPDIR
EPEN
DTGL
Bit
0
6
Endpoint Enable Bit
Set to enable the endpoint according to the device configuration. Endpoint 0
should always be enabled after a hardware or USB bus reset and participate in
the device configuration.
Clear to disable the endpoint according to the device configuration.
NAK Interrupt enable
Set this bit to enable NAK IN or NAK OUT interrupt.
Clear this bit to disable NAK IN or NAK OUT Interrupt.
NAK OUT received
This bit is set by hardware when an NAK handshake has been sent in response
of a OUT request from the Host. This triggers a USB interrupt when NAKIEN is
set.
This bit should be cleared by software.
NAK IN received
This bit is set by hardware when an NAK handshake has been sent in response
of a IN request from the Host. This triggers a USB interrupt when NAKIEN is set.
This bit should be cleared by software.
Data Toggle Status Bit (Read-only)
Set by hardware when a DATA1 packet is received.
Cleared by hardware when a DATA0 packet is received.
Endpoint Direction Bit
Set to configure IN direction for Bulk, Interrupt and Isochronous endpoints.
Clear to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.
This bit has no effect for Control endpoints.
Endpoint Type Bits
Set this field according to the endpoint configuration (Endpoint 0 should always
be configured as Control):
00
01
10
11
STALLRQ
Control endpoint
Isochronous endpoint
Bulk endpoint
Interrupt endpoint
5
TXRDY
4
STLCRC
3
RXSETUP
2
RXOUTB0
1
4109L–8051–02/08
)
TXCMP
0