AT89C51SND1C-7HTUL Atmel, AT89C51SND1C-7HTUL Datasheet - Page 62

• Manufacturer Part Number: AT89C51SND1C-7HTUL
• Description: IC MCU 64KB FLASH MEM 81-CBGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND1C-7HTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 81-CBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.3
12.3.1
62
Watchdog Operation
AT8xC51SND1C
WDT Behavior during Idle and Power-down Modes
After reset, the WDT is disabled. The WDT is enabled by writing the sequence 1Eh and E1h into
the WDTRST register. As soon as it is enabled, there is no way except the chip reset to disable
it. If it is not cleared using the previous sequence, the WDT overflows and forces a chip reset.
This overflow generates a high level 96 oscillator periods pulse on the RST pin to globally reset
the application (refer to Section “Power Management”, page 48).
The WDT time-out period can be adjusted using WTO2:0 bits located in the WDTPRG register
accordingly to the formula shown in Figure 12-3. In this formula, WTOval represents the decimal
value of WTO2:0 bits. Table 67 reports the time-out period depending on the WDT frequency.
Figure 12-3. WDT Time-Out Formula
Table 67. WDT Time-Out Computation
Notes:
Operation of the WDT during power reduction modes deserves special attention.
The WDT continues to count while the AT8xC51SND1C is in Idle mode. This means that you
must dedicate some internal or external hardware to service the WDT during Idle mode. One
approach is to use a peripheral Timer to generate an interrupt request when the Timer over-
flows. The interrupt service routine then clears the WDT, reloads the peripheral Timer for the
next service period and puts the AT8xC51SND1C back into Idle mode.
The Power-down mode stops all phase clocks. This causes the WDT to stop counting and to
hold its count. The WDT resumes counting from where it left off if the Power-down mode is ter-
minated by INT0, INT1 or keyboard interrupt. To ensure that the WDT does not overflow shortly
after exiting the Power-down mode, it is recommended to clear the WDT just before entering
Power-down mode.
The WDT is cleared and disabled if the Power-down mode is terminated by a reset.
1. These frequencies are achieved in X1 mode or in X2 mode when WTX2 = 1:
2. These frequencies are achieved in X2 mode when WTX2 = 0: F
WTO2 WTO1 WTO0
0
0
0
0
1
1
1
1
F
WDT
= F
0
0
1
1
0
0
1
1
OSC
÷ 2.
0
1
0
1
0
1
0
1
WDT
6 MHz
TO
131.07
262.14
524.29
16.38
32.77
65.54
1049
2097
=
(1)
6
⋅ ((
2
8 MHz
14
196.56
786.24
12.28
24.57
49.14
98.28
393.1
1572
F
⋅
WDT
2
WTOval
(1)
) – 1)
10 MHz
157.29
314.57
629.15
19.66
39.32
78.64
1258
9.83
F
(1)
WDT
(ms)
12 MHz
131.07
262.14
524.29
16.38
32.77
65.54
1049
8.19
WDT
(2)
= F
16 MHz
OSC
196.56
393.12
786.24
12.28
24.57
49.14
98.28
6.14
.
(2)
4109L–8051–02/08
20 MHz
157.29
314.57
629.15
19.66
39.32
78.64
4.92
9.83
(2)