EP9301-CQ Cirrus Logic Inc, EP9301-CQ Datasheet - Page 563

• Manufacturer Part Number: EP9301-CQ
• Description: IC ARM920T MCU 166MHZ 208-LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQ

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 598-1248

DS785UM1
15.2.4 Enabling Infrared (Ir) Modes
15.3.1 Clocking Requirements
15.3 UART2 Package Dependency
UART2 uses package pins RXD1 and TXD1. Pin RXD1 drives both the UART2 UART input
and the UART2 SIR input.
However, Syscon register DeviceCfg[28] (IonU2) controls what drives pin TXD1. See
Table
Therefore, to use any IrDA mode, FIR, MIR or SIR, set IonU2. To use UART2 as a UART,
clear IonU2.
There are two clocks, PCLK and UARTCLK.
UARTCLK frequency must accommodate the desired range of baud rates:
The frequency of UARTCLK must also be within the required error limits for all baud rates to
be used.
To allow sufficient time to write the received data to the receive FIFO, UARTCLK must be less
than or equal to four times the frequency of PCLK:
Disabled
UART2
15-2.
Mode
MIR
SIR
FIR
IonU2
0
1
DeviceCfg Register
U2EN
Fuartclk(min) >= 32 x baud_rate(max)
Fuartclk(max) <= 32 x 65,536 x baud_rate(min)
0
1
1
x
x
IonU2
Table 15-1. UART2 / IrDA Modes
Table 15-2. IonU2 Pin Function
UART2 UART is the output signal
Logical OR of IrDA output signal and UART2 SIR output signal
Copyright 2007 Cirrus Logic
0
1
1
1
x
SirEn
UART2Ctrl Register
0
0
1
0
0
Pin TXD1 Function
UARTE
0
1
1
0
0
IrEnable Register
EN[1]
0
0
0
1
1
EP93xx User’s Guide
EN[0]
0
0
1
0
1
UART2
15-5
15