STR912FW44X6 STMicroelectronics, STR912FW44X6 Datasheet - Page 10
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STR912FW44X6
Manufacturer Part Number
STR912FW44X6
Description
MCU 512K FLASH 96K SRAM USB CAN
Manufacturer
STMicroelectronics
Series
STR9r
Datasheet
1.STR910FM32X6.pdf
(73 pages)
Specifications of STR912FW44X6
Core Processor
ARM9
Core Size
32-Bit
Speed
96MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 2 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
For Use With
497-8267 - BOARD EVAL BASED ON STR9MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2497-5859 - EVAL BRD FULL USB DONGLE STR912MCBSTR9 - BOARD EVAL STM STR9 SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-5063-2
497-5063-2
497-5063-2ND
STR912FW44X6T
497-5063-2
497-5063-2ND
STR912FW44X6T
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STR912FW44X6
Manufacturer:
ST
Quantity:
20 000
Functional overview
2.5
2.5.1
2.5.2
2.6
2.7
10/73
SRAM (64K or 96K Bytes)
A 32-bit wide SRAM resides on the CPU’s Data TCM (D-TCM) interface, providing single-cycle
data accesses. As shown in
High-performance Bus (AHB). Sharing is controlled by simple arbitration logic to allow the DMA
unit on the AHB to also access to the SRAM.
Arbitration
Zero-wait state access occurs for either the D-TCM or the AHB when only one of the two is
requesting SRAM. When both request SRAM simultaneously, access is granted on an
interleaved basis so neither requestor is starved, granting one 32-bit word transfer to each
requestor before relinquishing SRAM to the other. When neither the D-TCM or the AHB are
requesting SRAM, the arbiter leaves access granted to the most recent user (if D-TCM was last
to use SRAM then the D-TCM will not have to arbitrate to get access next time).
The CPU may execute code from SRAM through the AHB. There are no wait states as long as
the D-TCM is not contending for SRAM access and the AHB is not sharing bandwidth with
peripheral traffic. The ARM966E-S CPU core has a small pre-fetch queue built into this
instruction path through the AHB to look ahead and fetch instructions during idle bus cycles.
Battery backup
When a battery is connected to the designated battery backup pin (VBATT), SRAM contents
are automatically preserved when the normal operating voltage on VDD pins is lost or sags
below threshold. Automatic switchover to SRAM can be disabled by firmware if it is desired that
the battery will power only the RTC and not the SRAM during standby.
DMA data movement
DMA channels on the Advanced High-performance Bus (AHB) take full advantage of the
separate data path provided by the Harvard architecture, moving data rapidly and largely
independent of the instruction path. There are two DMA units, one is dedicated to move data
between the Ethernet interface and SRAM, the other DMA unit has eight programmable
channels with 16 request signals to service other peripherals and interfaces (USB, SSP, I2C,
UART, Timers, EMI, and external request pins). Both single word and burst DMA transfers are
supported. Memory-to-memory transfers are supported in addition to memory-peripheral
transfers. DMA access to SRAM is shared with D-TCM accesses, and arbitration is described
in
tables. Of the 16 DMA request signals, two are assigned to external inputs. The DMA unit can
move data between external devices and resources inside the STR91xF through the EMI bus.
Non-volatile memories
There are two independent 32-bit wide Burst Flash memories enabling true read-while-write
operation. The Flash memories are single-voltage erase/program with 20 year minimum data
retention and 100K minimum erase cycles. The primary Flash memory is much larger than the
secondary Flash.
Both Flash memories are blank when devices are shipped from ST. The CPU can boot only
from Flash memory (configurable selection of which Flash bank).
Section
2.5.1. Efficient DMA transfers are managed by firmware using linked list descriptor
Figure
1, the D-TCM shares SRAM access with the Advanced
STR91xF