DSP56F805FV80 Freescale Semiconductor, DSP56F805FV80 Datasheet - Page 34

• Manufacturer Part Number: DSP56F805FV80
• Description: IC DSP 80MHZ 31.5K FLASH 144LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxr

Specifications of DSP56F805FV80

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 71KB (35.5K x 16)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
34
RESET Assertion to Address, Data and Control
Signals High Impedance
Minimum RESET Assertion Duration
OMR Bit 6 = 0
OMR Bit 6 = 1
RESET Deassertion to First External Address Output
Edge-sensitive Interrupt Request Width
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction
execution in the interrupt service routine
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State
IRQA Width Assertion to Recover from Stop State
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
RSTO pulse width
normal operation
internal reset mode
1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is
not the minimum required so that the IRQA interrupt is accepted.
4. The interrupt instruction fetch is visible on the pins only in Mode 3.
5. ET = External Clock period, For an external crystal frequency of 8MHz, ET=125ns.
6. Parameters listed are guaranteed by design.
• After power-on reset
• When recovering from Stop state
Operating Conditions:
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing
5
Characteristic
3
2
V
SS
= V
56F805 Technical Data, Rev. 16
SSA
= 0 V, V
4
DD
Symbol
t
t
t
RSTO
t
t
t
t
RDA
RAZ
IRW
t
t
IDM
t
IRQ
= V
t
RA
IRI
IW
t
IG
IF
II
DDA
= 3.0–3.6 V, T
2,097,151ET
275,000T
128T
63ET
1.5T
Min
33T
15T
16T
13T
2T
—
—
—
—
—
—
—
A
= –40° to +85°C, C
275,000T
275,000T
275,000T
Max
34T
12T
12T
12T
21
—
—
—
—
—
—
—
Freescale Semiconductor
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
L
≤
1, 6
50pF
Figure 3-12
Figure 3-12
Figure 3-12
Figure 3-13
Figure 3-14
Figure 3-14
Figure 3-15
Figure 3-16
Figure 3-16
Figure 3-17
Figure 3-17
Figure 3-18
See Figure