MC68HC11F1CPU4 Freescale Semiconductor, MC68HC11F1CPU4 Datasheet - Page 105

• Manufacturer Part Number: MC68HC11F1CPU4
• Description: IC MCU 512 EEPROM 4MHZ 80-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11F1CPU4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -

8.5.2 Serial Peripheral Status
SPSR — Serial Peripheral Status Register
SPIF — SPI Interrupt Complete Flag
WCOL — Write Collision
Bit 5 — Not implemented
MODF — Mode Fault
Bits [3:0] — Not implemented
8.5.3 Serial Peripheral Data Register
SPDR — SPI Data Register
TECHNICAL DATA
RESET:
SPIF is set upon completion of data transfer between the processor and the external
device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated.
To clear the SPIF bit, read the SPSR then access the SPDR. Unless SPSR is read
(with SPIF set) first, attempts to write SPDR are inhibited.
Clearing the WCOL bit is accomplished by reading the SPSR followed by an access of
SPDR. Refer to 8.3.4 Slave Select and 8.4 SPI System Errors.
Always reads zero
To clear the MODF bit, read the SPSR then write to the SPCR. Refer to 8.3.4 Slave
Select and 8.4 SPI System Errors.
Always read zero
The SPDR is used when transmitting or receiving data on the serial bus. Only a write
to this register initiates transmission or reception of a byte, and this only occurs in the
master device. At the completion of transferring a byte of data, the SPIF status bit is
set in both the master and slave devices.
A read of the SPDR is actually a read of a buffer. To prevent an overrun and the loss
of the byte that caused the overrun, the first SPIF must be cleared by the time a second
transfer of data from the shift register to the read buffer is initiated.
SPI is double buffered in and single buffered out.
0 = No write collision
1 = Write collision
0 = No mode fault
1 = Mode fault
SPIF
Bit 7
Bit 7
Bit 7
0
WCOL
6
0
6
6
Freescale Semiconductor, Inc.
For More Information On This Product,
SERIAL PERIPHERAL INTERFACE
—
5
0
5
5
Go to: www.freescale.com
MODF
4
0
4
4
—
3
0
3
3
—
2
0
2
2
—
1
0
1
1
Bit 0
Bit 0
Bit 0
—
0
$102A
$1029
8-7