MC68HC11F1CPU4 Freescale Semiconductor, MC68HC11F1CPU4 Datasheet - Page 87

• Manufacturer Part Number: MC68HC11F1CPU4
• Description: IC MCU 512 EEPROM 4MHZ 80-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11F1CPU4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -

7.1 Data Format
7.2 Transmit Operation
TECHNICAL DATA
The serial communications interface (SCI) is a universal asynchronous receiver trans-
mitter (UART), one of two independent serial I/O subsystems in the MC68HC11F1
MCU. It has a standard nonreturn to zero (NRZ) format (one start bit, eight or nine data
bits, and one stop bit). Several baud rates are available. The SCI transmitter and re-
ceiver are independent, but use the same data format and bit rate.
The serial data format requires the following conditions:
Selection of the word length is controlled by the M bit of SCI control register SCCR1.
The SCI transmitter includes a parallel transmit data register (SCDR) and a serial shift
register. The contents of the serial shift register can only be written through the SCDR.
This double buffered operation allows a character to be shifted out serially while an-
other character is waiting in the SCDR to be transferred into the serial shift register.
The output of the serial shift register is applied to TxD as long as transmission is in
progress or the transmit enable (TE) bit of serial communication control register 2
(SCCR2) is set. The block diagram, Figure 7-1, shows the transmit serial shift register
and the buffer logic at the top of the figure.
1. An idle-line in the high state before transmission or reception of a message.
2. A start bit, logic zero, transmitted or received, that indicates the start of each
3. Data that is transmitted and received least significant bit (LSB) first.
4. A stop bit, logic one, used to indicate the end of a frame. (A frame consists of a
5. A break (defined as the transmission or reception of a logic zero for some mul-
character.
start bit, a character of eight or nine data bits, and a stop bit.)
tiple number of frames).
SECTION 7 SERIAL COMMUNICATIONS INTERFACE
Freescale Semiconductor, Inc.
For More Information On This Product,
SERIAL COMMUNICATIONS INTERFACE
Go to: www.freescale.com
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