MC68HC908GR8CFA Freescale Semiconductor, MC68HC908GR8CFA Datasheet - Page 105

• Manufacturer Part Number: MC68HC908GR8CFA
• Description: IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GR8CFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

MC68HC908GR8 — Rev 4.0
MOTOROLA
to use as the source for the base clock. (See
Circuit.) If the VCO is selected as the source for the base clock and the
LOCK bit is clear, the PLL has suffered a severe noise hit and the
software must take appropriate action, depending on the application.
(See
The following conditions apply when the PLL is in automatic bandwidth
control mode:
The PLL also may operate in manual mode (AUTO = 0). Manual mode is
used by systems that do not require an indicator of the lock condition for
proper operation. Such systems typically operate well below f
The following conditions apply when in manual mode:
Freescale Semiconductor, Inc.
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For More Information On This Product,
Interrupts
The ACQ bit (see
indicator of the mode of the filter. (See
Modes.)
The ACQ bit is set when the VCO frequency is within a certain
tolerance and is cleared when the VCO frequency is out of a
certain tolerance. (See
more information.)
The LOCK bit is a read-only indicator of the locked state of the PLL.
The LOCK bit is set when the VCO frequency is within a certain
tolerance and is cleared when the VCO frequency is out of a
certain tolerance. (See
more information.)
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s
lock condition changes, toggling the LOCK bit. (See
Register.)
ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.
Before entering tracking mode (ACQ = 1), software must wait a
given time, t
turning on the PLL by setting PLLON in the PLL control register
(PCTL).
Clock Generator Module (CGMC)
Go to: www.freescale.com
for information and precautions on using interrupts.)
ACQ
(see
PLL Bandwidth Control
Acquisition/Lock Time
Acquisition/Lock Time Specifications
Acquisition/Lock Time Specifications
Clock Generator Module (CGMC)
Acquisition and Tracking
Base Clock Selector
Register) is a read-only
Specifications), after
Functional Description
PLL Control
Technical Data
BUSMAX
for
for
105
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