MC68HRC908JK3CP Freescale Semiconductor, MC68HRC908JK3CP Datasheet - Page 122

• Manufacturer Part Number: MC68HRC908JK3CP
• Description: IC MCU FLASH 8B 8MHZ RC 4K 20DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HRC908JK3CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Connectivity: -

Timer Interface Module (TIM)
10.5.3.1 Unbuffered Output Compare
10.5.3.2 Buffered Output Compare
Technical Data
120
Any output compare channel can generate unbuffered output compare
pulses as described in
unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an
output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass
the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
output compare value on channel x:
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the TCH0 pin. The TIM channel
registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The output compare value in the TIM
•
•
When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
When changing to a larger output compare value, enable
channel x TIM overflow interrupts and write the new value in the
TIM overflow interrupt routine. The TIM overflow interrupt occurs
at the end of the current counter overflow period. Writing a larger
value in an output compare interrupt routine (at the end of the
current pulse) could cause two output compares to occur in the
same counter overflow period.
Timer Interface Module (TIM)
10.5.3 Output
Compare. The pulses are
MC68H(R)C908JL3
Freescale Semiconductor
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Rev. 1.1