MC68HRC908JK3CP Freescale Semiconductor, MC68HRC908JK3CP Datasheet - Page 134
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MC68HRC908JK3CP
Manufacturer Part Number
MC68HRC908JK3CP
Description
IC MCU FLASH 8B 8MHZ RC 4K 20DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68HC908JK1CDW.pdf
(212 pages)
Specifications of MC68HRC908JK3CP
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LED, LVD, POR, PWM
Number Of I /o
15
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HRC908JK3CP
Manufacturer:
FREECAL
Quantity:
20 000
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Timer Interface Module (TIM)
Technical Data
132
Figure 10-7. TIM Channel Status and Control Registers (TSC0:TSC1)
Address:
Address:
CHxF — Channel x Flag Bit
CHxIE — Channel x Interrupt Enable Bit
Reset:
Reset:
Read:
Write:
Read:
Write:
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIM
counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE=1), clear
CHxF by reading the TIM channel x status and control register with
CHxF set and then writing a logic zero to CHxF. If another interrupt
request occurs before the clearing sequence is complete, then writing
logic zero to CHxF has no effect. Therefore, an interrupt request
cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic one to CHxF has no effect.
This read/write bit enables TIM CPU interrupt service requests on
channel x. Reset clears the CHxIE bit.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
$0025
$0028
CH0F
CH1F
Bit 7
Bit 7
0
0
0
0
Timer Interface Module (TIM)
CH0IE
CH1IE
= Unimplemented
TSC0
TSC1
6
0
6
0
MS0B
5
0
5
0
0
MS0A
MS1A
4
0
4
0
ELS0B
ELS1B
3
0
3
0
MC68H(R)C908JL3
ELS0A
ELS1A
Freescale Semiconductor
2
0
2
0
TOV0
TOV1
1
0
1
0
—
CH0MAX
CH1MAX
Rev. 1.1
Bit 0
Bit 0
0
0
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