MC68HRC908JK3CP Freescale Semiconductor, MC68HRC908JK3CP Datasheet - Page 200

• Manufacturer Part Number: MC68HRC908JK3CP
• Description: IC MCU FLASH 8B 8MHZ RC 4K 20DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HRC908JK3CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Connectivity: -

Electrical Specifications
18.10 3V Control Timing
Technical Data
198
NOTES:
Internal operating frequency
RST input pulse width low
1. V
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this infor-
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
noted.
mation.
NOTES:
1. V
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I
4. Wait I
5. STOP I
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum V
8. R
DD
than 100 pF on all outputs. C
run I
less than 100 pF on all outputs. C
fects wait I
minimum V
DD
PU1
= 2.7 to 3.3 Vdc, V
= 2.7 to 3.3 Vdc, V
DD
and R
DD
. Measured with all modules enabled.
DD
measured using external square wave clock source (f
measured with OSC1 grounded, no port pins sourcing current. LVI is disabled.
DD
DD
PU2
DD
.
Characteristic
is reached.
are measured at V
DD
is not reached before the internal POR reset is released,
Characteristic
measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less
SS
(3)
= 0 Vdc, T
SS
Table 18-7. DC Electrical Characteristics (3V)
(2)
= 0 Vdc, T
L
(1)
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
A
L
Table 18-8. Control Timing (3V)
DD
= 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly af-
= T
(1)
A
= 5.0V
= T
L
to T
L
Electrical Specifications
to T
H
; timing shown with respect to 20% V
H
, unless otherwise noted.
Symbol
OP
Symbol
= 4MHz); all inputs 0.2 V from rail; no dc loads;
t
f
OP
IRL
Min
RST
must be driven low externally until
Min
DD
1.5
—
Typ
MC68H(R)C908JL3
and 70% V
(2)
Freescale Semiconductor
Max
DD
—
4
Max
, unless otherwise
—
MHz
Unit
Rev. 1.1
Unit
µs