MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 212

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Burst Buffer Controller 2 Module
When no match happens, the effective region is the global region.
The region attribute registers contain the region protection fields: PP, G, and CMPR. The protection fields
are compared to address attributes issued by the RCPU. If the access is permitted, the address is passed to
the BIU and further to the U-bus.
Whenever the IMPU detects access violation, the following actions are taken:
However, if the required address contains a show cycle attribute, the BIU delivers the access onto the
U-bus to obtain program tracking.
The exception vector (address) that the RCPU issues for this exception has a 0x1300 offset in the RCPU
exception vector table. The access violation status is provided in the RCPU SRR1 special purpose register.
The encoding of the status bits is as follows:
Only one bit is set at a time.
4.2.4
The BBC is operating as a U-bus slave when the IMPU registers, decompressor RAM (DECRAM) or
ICDU registers are accessed from the U-bus. The IMPU register programming is done using PowerPC ISA
mtspr/mfspr instructions. The ICDU configuration registers (DCCRs) and DECRAM are mapped into the
chip memory space and accessed by load/store instructions. DCCR and DECRAM accesses may be
disabled by BBCMCR[DCAE]. Refer to
(BBCMCR).”
4.2.5
Upon soft reset, the BBC switches to an idle state and all pending U-bus accesses are ignored, the ICDU
internal queue is flushed and the IMPU switches to a disabled state where all memory space is accessible
for both user and supervisor.
Hard reset sets some of the fields and bits in the BBC configuration registers to their default reset state.
Some bits in the BBCMCR register get their values from the reset configuration word.
All the registers are reset using HRESET; SRESET alone has no effect on them.
4-6
1. The request forwarded to the BIU is canceled
2. The RCPU is informed that the requested address caused an access violation by exception request.
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•
•
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SRR1 [1] = 0
SRR1 [3] = Guarded storage
SRR1 [4] = Protected storage or compression violation
SRR1 [10] = 0
Slave Operation
Reset Behavior
MPC561/MPC563 Reference Manual, Rev. 1.2
Section 4.6.2.1, “BBC Module Configuration Register
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