MC68HRC98JK3ECDW Freescale Semiconductor, MC68HRC98JK3ECDW Datasheet - Page 169
![IC MCU 4K FLASH 8MHZ 20-SOIC](/photos/6/50/65027/375-20-soic_sml.jpg)
MC68HRC98JK3ECDW
Manufacturer Part Number
MC68HRC98JK3ECDW
Description
IC MCU 4K FLASH 8MHZ 20-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908JK1ECDWE.pdf
(180 pages)
Specifications of MC68HRC98JK3ECDW
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LED, LVD, POR, PWM
Number Of I /o
15
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HRC98JK3ECDW
Manufacturer:
MOTOROLA
Quantity:
2 880
Part Number:
MC68HRC98JK3ECDW
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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SSREC — Short Stop Recovery Bit
STOP — STOP Instruction Enable
COPD — COP Disable Bit
B.5.3 Mask Option Register 2 (MOR2)
IRQPUD — IRQ Pin Pull-up control bit
LVIT1, LVIT0 — Low Voltage Inhibit trip voltage selection bits
B.6 Monitor ROM
The monitor program (monitor ROM: $FE10–$FFCF) on the MC68H(R)C08JL3E/JK3E is for device
testing only. $FC00–$FDFF are unused.
Freescale Semiconductor
SSREC enables the CPU to exit stop mode with a delay of 32 × 2OSCOUT cycles instead of a
4096 × 2OSCOUT cycle delay.
STOP enables the STOP instruction.
COPD disables the COP module. (See
Detail description of the LVI control signals is given in
1 = Stop mode recovery after 32 × 2OSCOUT cycles
0 = Stop mode recovery after 4096 × 2OSCOUT cycles
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
1 = COP module disabled
0 = COP module enabled
1 = Internal pull-up is disconnected
0 = Internal pull-up is connected between IRQ pin and V
Address:
Reset:
Read:
Write:
POR:
Exiting stop mode by pulling reset will result in the long stop recovery.
IRQPUD
$001E
Bit 7
0
0
If using an external crystal, do not set the SSREC bit.
Figure 18-2. Mask Option Register 2 (MOR2)
= Unimplemented
MC68HC908JL3E Family Data Sheet, Rev. 4
6
0
0
0
Chapter 13 Computer Operating Properly
5
0
0
0
NOTE
affected
LVIT1
Not
4
0
Chapter 14 Low Voltage Inhibit (LVI)
affected
LVIT0
Not
3
0
DD
2
0
0
0
1
0
0
0
Bit 0
0
0
0
(COP).)
169
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