MC68HRC98JK3ECDW Freescale Semiconductor, MC68HRC98JK3ECDW Datasheet - Page 48
![IC MCU 4K FLASH 8MHZ 20-SOIC](/photos/6/50/65027/375-20-soic_sml.jpg)
MC68HRC98JK3ECDW
Manufacturer Part Number
MC68HRC98JK3ECDW
Description
IC MCU 4K FLASH 8MHZ 20-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908JK1ECDWE.pdf
(180 pages)
Specifications of MC68HRC98JK3ECDW
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LED, LVD, POR, PWM
Number Of I /o
15
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HRC98JK3ECDW
Manufacturer:
MOTOROLA
Quantity:
2 880
Part Number:
MC68HRC98JK3ECDW
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
INH Inherent
IMM Immediate
DIR Direct
EXT Extended
DD
IX+D Indexed-Direct
*
LSB
Pre-byte for stack pointer indexed instructions
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
MSB
Direct-Direct
BRSET0
3
BRCLR0
3
BRSET1
3
BRCLR1
3
BRSET2
3
BRCLR2
3
BRSET3
3
BRCLR3
3
BRSET4
3
BRCLR4
3
BRSET5
3
BRCLR5
3
BRSET6
3
BRCLR6
3
BRSET7
3
BRCLR7
3
Bit Manipulation
DIR
0
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BSET0
BCLR0
BSET1
BCLR1
BSET2
BCLR2
BSET3
BCLR3
BSET4
BCLR4
BSET5
BCLR5
BSET6
BCLR6
BSET7
BCLR7
DIR
REL Relative
IX
IX1
IX2
IMD Immediate-Direct
DIX+ Direct-Indexed
1
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Indexed, No Offset
Indexed, 8-Bit Offset
Indexed, 16-Bit Offset
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Branch
BHCC
BHCS
BMC
BMS
REL
BRA
BRN
BCC
BCS
BNE
BEQ
BLS
BPL
BMI
BHI
BIL
BIH
2
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
3
2
2
2
2
2
2
2
2
3
2
2
2
CBEQ
DBNZ
STHX
COM
NEG
ROR
ASR
ROL
DEC
LSR
TST
CLR
DIR
LSL
INC
3
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
4
5
4
4
4
4
4
4
4
4
5
4
3
3
1
3
1
1
1
3
1
1
1
1
1
2
1
1
3
1
CBEQA
DBNZA
COMA
NEGA
RORA
DECA
LSRA
LDHX
ASRA
ROLA
CLRA
LSLA
INCA
TSTA
MUL
MOV
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+
IX1+ Indexed, 1-Byte Offset with
INH
4
INH
IMM
INH
INH
INH
IMM
INH
INH
INH
INH
INH
INH
INH
INH
DD
INH
1
4
5
1
1
3
1
1
1
1
1
3
1
1
5
1
Indexed, No Offset with
Post Increment
Post Increment
Read-Modify-Write
1
3
1
1
1
2
1
1
1
1
1
2
1
1
2 DIX+
1
CBEQX
DBNZX
NEGX
COMX
RORX
LSRX
LDHX
ASRX
ROLX
DECX
CLRX
LSLX
INCX
TSTX
MOV
INH
DIV
5
INH
IMM
INH
INH
INH
DIR
INH
INH
INH
INH
INH
INH
INH
INH
INH
1
4
7
1
1
4
1
1
1
1
1
3
1
1
4
1
2
3 IX1+
1
2
2
3
2
2
2
2
2
3
2
2
3
2
CBEQ
CPHX
DBNZ
COM
MOV
NEG
NSA
ROR
ASR
ROL
DEC
CLR
LSR
LSL
TST
INC
IX1
6
INH
IX1
IX1
IMM
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IMD
IX1
4
5
3
4
4
3
4
4
4
4
4
5
4
3
4
3
IX1
Table 4-2. Opcode Map
3
4
3
3
3
3
3
3
3
4
3
3
3
CBEQ
DBNZ
COM
NEG
ROR
DEC
SP1
LSR
ASR
ROL
TST
CLR
9E6
LSL
INC
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
5
6
5
5
5
5
5
5
6
5
4
4
5
1
2
1
1
1
2
1
1
1
1
1
2
1
1
2 IX+D
1
CBEQ
CPHX
DBNZ
NEG
COM
ROR
MOV
DAA
LSR
ASR
ROL
DEC
CLR
LSL
INC
TST
Low Byte of Opcode in Hexadecimal
IX
7
IX
IX+
INH
IX
IX
DIR
IX
IX
IX
IX
IX
IX
IX
IX
IX
3
4
2
3
3
4
3
3
3
3
3
4
3
2
4
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PSHA
PSHX
PULH
PSHH
CLRH
STOP
PULA
PULX
WAIT
RTS
SWI
TAP
TPA
INH
RTI
8
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
7
4
9
2
1
2
2
2
2
2
2
1
1
1
Control
2
2
2
2
1
1
1
1
1
1
1
1
1
1
BGE
BGT
SEC
RSP
NOP
BLE
TXS
TSX
TAX
CLC
TXA
INH
BLT
SEI
CLI
9
*
REL
REL
REL
REL
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
3
3
3
3
2
2
1
1
1
2
2
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
CMP
AND
EOR
ADC
ORA
ADD
IMM
SUB
SBC
CPX
LDA
BSR
LDX
BIT
AIS
AIX
A
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
REL
IMM
IMM
2
2
2
2
2
2
2
2
2
2
2
2
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
LSB
CMP
SUB
SBC
CPX
AND
EOR
ADC
ORA
ADD
JMP
LDA
STA
JSR
LDX
STX
DIR
BIT
B
0
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
MSB
3
3
3
3
3
3
3
3
3
3
3
3
2
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
BRSET0
3
SUB
CMP
SBC
CPX
AND
EOR
ADC
ORA
ADD
EXT
LDA
STA
JMP
JSR
LDX
STX
BIT
C
0
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
DIR
4
4
4
4
4
4
4
4
4
4
4
4
3
5
4
4
5
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
High Byte of Opcode in Hexadecimal
Cycles
Opcode Mnemonic
Number of Bytes / Addressing Mode
Register/Memory
CMP
AND
EOR
ADC
ORA
ADD
SUB
SBC
CPX
LDA
JMP
JSR
LDX
STX
STA
IX2
BIT
D
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
4
4
4
4
4
4
4
4
4
4
4
4
4
6
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
CMP
EOR
ORA
9ED
SUB
SBC
CPX
AND
ADC
ADD
LDX
STX
SP2
LDA
STA
BIT
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
5
5
5
5
5
5
5
5
5
5
5
5
5
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
CMP
SUB
SBC
CPX
AND
EOR
ADC
ORA
ADD
JMP
LDA
STA
JSR
LDX
STX
BIT
IX1
E
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
3
3
3
3
3
3
3
3
3
3
3
3
3
5
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
SUB
CMP
SBC
CPX
AND
EOR
ADC
ORA
ADD
SP1
9EE
LDA
LDX
STX
STA
BIT
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CMP
EOR
ORA
SUB
SBC
CPX
AND
ADC
ADD
JMP
LDX
STX
LDA
STA
JSR
BIT
IX
F
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
2
2
2
2
2
2
2
2
2
2
2
2
2
4
2
2