MC68HRC98JK3ECDW Freescale Semiconductor, MC68HRC98JK3ECDW Datasheet - Page 92
![IC MCU 4K FLASH 8MHZ 20-SOIC](/photos/6/50/65027/375-20-soic_sml.jpg)
MC68HRC98JK3ECDW
Manufacturer Part Number
MC68HRC98JK3ECDW
Description
IC MCU 4K FLASH 8MHZ 20-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908JK1ECDWE.pdf
(180 pages)
Specifications of MC68HRC98JK3ECDW
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LED, LVD, POR, PWM
Number Of I /o
15
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HRC98JK3ECDW
Manufacturer:
MOTOROLA
Quantity:
2 880
Part Number:
MC68HRC98JK3ECDW
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Timer Interface Module (TIM)
8.9.4 TIM Channel Status and Control Registers (TSC0:TSC1)
Each of the TIM channel status and control registers does the following:
CHxF — Channel x Flag Bit
CHxIE — Channel x Interrupt Enable Bit
92
•
•
•
•
•
•
•
•
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE=1), clear CHxF by reading the TIM channel x
status and control register with CHxF set and then writing a zero to CHxF. If another interrupt request
occurs before the clearing sequence is complete, then writing zero to CHxF has no effect. Therefore,
an interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a one to CHxF has no effect.
This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE
bit.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
Flags input captures and output compares
Enables input capture and output compare interrupts
Selects input capture, output compare, or PWM operation
Selects high, low, or toggling output on output compare
Selects rising edge, falling edge, or any edge as the active input capture trigger
Selects output toggling on TIM overflow
Selects 0% and 100% PWM duty cycle
Selects buffered or unbuffered output compare/PWM operation
Address:
Address:
Reset:
Reset:
Read:
Read:
Figure 8-7. TIM Channel Status and Control Registers (TSC0:TSC1)
Write:
Write:
$0025
$0028
CH0F
CH1F
Bit 7
Bit 7
0
0
0
0
= Unimplemented
CH0IE
CH1IE
TSC0
TSC1
MC68HC908JL3E Family Data Sheet, Rev. 4
6
0
6
0
MS0B
5
0
5
0
0
MS0A
MS1A
4
0
4
0
ELS0B
ELS1B
3
0
3
0
ELS0A
ELS1A
2
0
2
0
TOV0
TOV1
1
0
1
0
Freescale Semiconductor
CH0MAX
CH1MAX
Bit 0
Bit 0
0
0