XC68HC705B32CB Freescale Semiconductor, XC68HC705B32CB Datasheet - Page 84

• Manufacturer Part Number: XC68HC705B32CB
• Description: IC MCU 2.1MHZ 32K OTP 56-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of XC68HC705B32CB

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 256 x 8
• Ram Size: 528 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-SDIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6
CPOL – Clock polarity
This bit allows the user to select the polarity of the clocks to be sent to the SCLK pin. It works in
conjunction with the CPHA bit to produce the desired clock-data relation (see
Figure
This bit should not be manipulated while the transmitter is enabled.
CPHA – Clock phase
This bit allows the user to select the phase of the clocks to be sent to the SCLK pin. This bit works
in conjunction with the CPOL bit to produce the desired clock-data relation (see
Figure
This bit should not be manipulated while the transmitter is enabled.
Freescale
6-12
(CPOL = 1, CPHA = 1)
(CPOL = 0, CPHA = 0)
(CPOL = 0, CPHA = 1)
(CPOL = 1, CPHA = 0)
6-10).
6-10).
1 (set)
0 (clear) –
1 (set)
0 (clear) –
clock
clock
clock
clock
data
Idle or preceding
transmission
–
–
Steady high value at SCLK pin outside transmission window.
Steady low value at SCLK pin outside transmission window.
SCLK clock line activated at beginning of data bit.
SCLK clock line activated in middle of data bit.
Figure 6-9 SCI data clock timing diagram (M=0)
Start
Start
SERIAL COMMUNICATIONS INTERFACE
LSB
0
1
2
M = 0 (8 data bits)
3
*
LBCL bit controls last data clock
4
5
6
MSB
*
*
7
*
*
Stop
Stop
Figure 6-9
Figure 6-9
MC68HC05B6
Idle or next
transmission
Rev. 4.1
and
and