XC68HC705B32CB Freescale Semiconductor, XC68HC705B32CB Datasheet - Page 96

• Manufacturer Part Number: XC68HC705B32CB
• Description: IC MCU 2.1MHZ 32K OTP 56-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of XC68HC705B32CB

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 256 x 8
• Ram Size: 528 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-SDIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7
The D/A converter has two data registers associated with it, PLMA and PLMB.
This is a dual 8-bit resolution D/A converter associated with two output pins (PLMA and PLMB).
The outputs are pulse length modulated signals whose duty cycle ratio may be modified. These
signals can be used directly as PLMs, or the filtered average may be used as general purpose
analog outputs.
The longest repetition period is 4096 times the programmable timer clock period (CPU clock
multiplied by four), and the shortest repetition period is 256 times the programmable timer clock
period (the repetition rate frequencies for a 4 MHz crystal are 122 Hz and 1953 Hz respectively).
Registers PLMA ($0A) and PLMB ($0B) are associated with the pulse length values of the two
counters. A value of $00 loaded into these registers results in a continuously low output on the
corresponding D/A output pin. A value of $80 results in a 50% duty cycle output, and so on, to the
maximum value $FF corresponding to an output which is at ‘1’ for 255/256 of the cycle. When the
MCU makes a write to register PLMA or PLMB the new value will only be picked up by the D/A
converters at the end of a complete cycle of conversion. This results in a monotonic change of the
DC component at the output without overshoots or vicious starts (a vicious start is an output which
gives totally erroneous PLM during the period immediately following an update of the PLM D/A
registers). This feature is achieved by double buffering of the PLM D/A registers. Examples of
PWM output waveforms are shown in
Freescale
7-2
Pulse length modulation A (PLMA)
Pulse length modulation B (PLMB)
$FF
$00
$01
$80
T = 4 CPU clocks in fast mode and 64 CPU clocks in slow mode
T
128 T
Figure 7-2 PLM output waveform examples
Address
PULSE LENGTH D/A CONVERTERS
$000A
$000B
bit 7
Figure
256 T
255 T
255 T
bit 6
7-2.
bit 5
bit 4
128 T
bit 3
bit 2
bit 1
T
MC68HC05B6
bit 0
0000 0000
0000 0000
Rev. 4.1
on reset
State