MC68HC908AP8CB Freescale Semiconductor, MC68HC908AP8CB Datasheet - Page 302
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MC68HC908AP8CB
Manufacturer Part Number
MC68HC908AP8CB
Description
IC MCU 8K FLASH 8MHZ 42SDIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AP8CFBE.pdf
(324 pages)
Specifications of MC68HC908AP8CB
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SCI, SPI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Electrical Specifications
22.6 5V Control Timing
300
Pullup resistors
Low-voltage inhibit, trip falling voltage1
Low-voltage inhibit, trip rising voltage1
Low-voltage inhibit, trip voltage2
V
Internal operating frequency
RST input pulse width low
1. V
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I
4. Wait I
5. STOP I
6. STOP I
7. Maximum is highest voltage that POR is guaranteed. The rearm voltage is triggered by V
8. If minimum V
9. R
10. Values are not affected by operating V
11. Measured from V
1. V
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this in-
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
REG
PTD[0:7]
RST, IRQ1, IRQ2
on all outputs; C
with all modules enabled.
C
V
formation.
DD
DD
DD
PU1
L
(10), (11)
= 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects wait I
= 4.5 to 5.5 Vdc, V
is reached.
= 4.5 to 5.5 Vdc, V
DD
and R
DD
DD
measured using external 32MHz to OSC1; all inputs 0.2 V from rail; no dc loads; less than 100 pF on all outputs.
measured using external 32.768kHz clock to OSC1; no port pins sourcing current.
measured with OSC1 grounded; no port pins sourcing current.
PU2
(9)
DD
are measured at V
is not reached before the internal POR reset is released,
DD
L
Characteristic
= 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects run I
DD
measured using external 32MHz clock to OSC1; all inputs 0.2 V from rail; no dc loads; less than 100pF
= V
Characteristic
(3)
SS
SS
TRIPF1
(2)
= 0 Vdc; timing shown with respect to 20% V
= 0 Vdc, T
(10)
Table 22-4. DC Electrical Characteristics (5V)
(Min) to 5.5 V.
(1)
DD
(10)
(10)
A
MC68HC908AP Family Data Sheet, Rev. 4
= 5.0V
(1)
= T
Table 22-5. Control Timing (5V)
DD
L
; they are the same for 3V and 5V.
to T
H
, unless otherwise noted.
Symbol
V
V
V
V
R
R
TRIPR1
TRIPF1
TRIPF2
REG
PU1
PU2
Symbol
DD
RST
t
f
IRL
OP
and 70% V
2.25
2.35
2.25
2.25
Min
21
21
must be driven low externally until minimum
DD
Min
750
—
, unless otherwise noted.
REG
Typ
2.45
2.55
2.45
2.50
27
27
DD
.
(2)
.
Freescale Semiconductor
Max
—
8
Max
2.65
2.75
2.65
2.75
39
39
DD
; measured
MHz
Unit
ns
Unit
kΩ
kΩ
V
V
V
V
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