MC908SR12CFAE Freescale Semiconductor, MC908SR12CFAE Datasheet - Page 29
![IC MCU 12K FLASH 8MHZ 48-LQFP](/photos/12/45/124574/mc908sr12cfae_sml.jpg)
MC908SR12CFAE
Manufacturer Part Number
MC908SR12CFAE
Description
IC MCU 12K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908SR12MFAE.pdf
(404 pages)
Specifications of MC908SR12CFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, Temp Sensor
Number Of I /o
31
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908SR12CFAE
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MC908SR12CFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC908SR12CFAE
Manufacturer:
FREESCALE
Quantity:
20 000
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MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
Freescale Semiconductor
Figure
17-1 MMIIC I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . 294
17-2 Multi-Master IIC Bus Transmission Signal Diagram . . . . . . . . 295
17-3 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
17-4 MMIIC Address Register (MMADR) . . . . . . . . . . . . . . . . . . . . 299
17-5 MMIIC Control Register 1 (MMCR1). . . . . . . . . . . . . . . . . . . .301
17-6 MMIIC Control Register 2 (MMCR2). . . . . . . . . . . . . . . . . . . .303
17-7 MMIIC Status Register (MMSR) . . . . . . . . . . . . . . . . . . . . . . . 305
17-8 MMIIC Data Transmit Register (MMDTR) . . . . . . . . . . . . . . . 307
17-9 MMIIC Data Receive Register (MMDRR) . . . . . . . . . . . . . . . . 308
17-10 MMIIC CRC Data Register (MMCRCDR) . . . . . . . . . . . . . . . . 309
17-11 MMIIC Frequency Divider Register (MMFDR) . . . . . . . . . . . . 310
17-12 Data Transfer Sequences for Master/Slave
17-13 Quick Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
17-14 Send Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
17-15 Receive Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
17-16 Write Byte/Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
17-17 Read Byte/Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
17-18 Process Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
17-19 Block Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
17-20 SMBus Protocol Implementation . . . . . . . . . . . . . . . . . . . . . . 316
18-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .318
18-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . 320
18-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . 321
18-4 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
18-5 Port A LED Control Register (LEDA) . . . . . . . . . . . . . . . . . . . 323
18-6 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . 324
18-7 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . 325
18-8 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
18-9 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . . 327
18-10 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . 329
18-11 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
18-12 Port A LED Control Register (LEDA) . . . . . . . . . . . . . . . . . . . 330
18-13 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . 331
18-14 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . . 332
18-15 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 312
List of Figures
Title
List of Figures
Data Sheet
Page
29
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