MC908SR12CFAE Freescale Semiconductor, MC908SR12CFAE Datasheet - Page 95
![IC MCU 12K FLASH 8MHZ 48-LQFP](/photos/12/45/124574/mc908sr12cfae_sml.jpg)
MC908SR12CFAE
Manufacturer Part Number
MC908SR12CFAE
Description
IC MCU 12K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908SR12MFAE.pdf
(404 pages)
Specifications of MC908SR12CFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, Temp Sensor
Number Of I /o
31
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908SR12CFAE
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MC908SR12CFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC908SR12CFAE
Manufacturer:
FREESCALE
Quantity:
20 000
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MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
Freescale Semiconductor
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
MUL
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
NOP
NSA
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
PSHA
PSHH
PSHX
PULA
PULH
PULX
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
Source
Form
Logical Shift Right
Move
Unsigned multiply
Negate (Two’s Complement)
No Operation
Nibble Swap A
Inclusive OR A and M
Push A onto Stack
Push H onto Stack
Push X onto Stack
Pull A from Stack
Pull H from Stack
Pull X from Stack
Rotate Left through Carry
Operation
Table 6-1. Instruction Set Summary (Continued)
Central Processor Unit (CPU)
H:X ← (H:X) + 1 (IX+D, DIX+)
0
(M)
Push (A); SP ← (SP) – 1
Push (H); SP ← (SP) – 1
Push (X); SP ← (SP) – 1
SP ← (SP + 1); Pull (H)
SP ← (SP + 1); Pull (A)
SP ← (SP + 1); Pull (X)
C
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
A ← (A[3:0]:A[7:4])
Destination
b7
X:A ← (X) × (A)
A ← (A) | (M)
b7
Description
None
← (M)
b0
Source
b0
C
V H I N Z C
0 – –
– 0 – – – 0 INH
– – – – – – INH
0 – –
– – – – – – INH
– – – – – – INH
– – – – – – INH
– – – – – – INH
– – – – – – INH
– – – – – – INH
– – – – – – INH
– – 0
– –
– –
Effect on
CCR
Central Processor Unit (CPU)
–
–
DIR
INH
INH
IX1
IX
SP1
DD
DIX+
IMD
IX+D
DIR
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
9EDA
9EEA
9E64
9E60
9E69
AA
BA
CA
DA
EA
4E
5E
6E
7E
9D
FA
8B
8A
34
44
54
64
74
42
30
40
50
60
70
62
87
89
86
88
39
49
59
69
79
Opcode Map
Data Sheet
dd
ff
ff
dd dd
dd
ii dd
dd
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
95
4
1
1
4
3
5
5
4
4
4
5
4
1
1
4
3
5
1
3
2
3
4
4
3
2
4
5
2
2
2
2
2
2
4
1
1
4
3
5
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