MC908SR12CFAE Freescale Semiconductor, MC908SR12CFAE Datasheet - Page 308
![IC MCU 12K FLASH 8MHZ 48-LQFP](/photos/12/45/124574/mc908sr12cfae_sml.jpg)
MC908SR12CFAE
Manufacturer Part Number
MC908SR12CFAE
Description
IC MCU 12K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908SR12MFAE.pdf
(404 pages)
Specifications of MC908SR12CFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, Temp Sensor
Number Of I /o
31
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Price
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MC908SR12CFAE
Manufacturer:
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MC908SR12CFAE
Manufacturer:
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Multi-Master IIC Interface (MMIIC)
17.7.6 MMIIC Data Receive Register (MMDRR)
Data Sheet
308
Address:
If the calling master does not return an acknowledge bit (MMRXAK = 1),
the module will release the SDA line for master to generate a STOP or
repeated START condition. The data in the MMDTR will not be
transferred to the output circuit until the next calling from a master. The
transmit buffer empty flag remains cleared (MMTXBE = 0).
In master mode, the data in MMDTR will be transferred to the output
circuit when:
If the slave does not return an acknowledge bit (MMRXAK = 1), the
master will generate a STOP or repeated START condition. The data in
the MMDTR will not be transferred to the output circuit. The transmit
buffer empty flag remains cleared (MMTXBE = 0).
The sequence of events for slave transmit and master transmit are
illustrated in
When the MMIIC module is enabled, MMEN = 1, data in this read-only
register depends on whether module is in master or slave mode.
In slave mode, the data in MMDRR is:
Reset:
Read: MMRD7
Write:
•
•
the module receives an acknowledge bit (MMRXAK = 0), after
setting master transmit mode (MMRW = 0), and the calling
address has been transmitted; or
the previous data in the output circuit has be transmitted and the
receiving slave returns an acknowledge bit, indicated by a
received acknowledge bit (MMRXAK = 0).
Figure 17-9. MMIIC Data Receive Register (MMDRR)
$004D
Bit 7
Multi-Master IIC Interface (MMIIC)
0
Figure
= Unimplemented
MMRD6
6
0
17-12.
MMRD5
5
0
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
MMRD4
4
0
MMRD3
3
0
MMRD2
Freescale Semiconductor
2
0
MMRD1
1
0
MMRD0
Bit 0
0
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