MCHLC908QY2CPE Freescale Semiconductor, MCHLC908QY2CPE Datasheet - Page 139

• Manufacturer Part Number: MCHLC908QY2CPE
• Description: IC MCU 1.5K FLASH 8MHZ 16-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHLC908QY2CPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 2MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

15.2.2.3 Break Auxiliary Register
The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the
MCU is in a state of break interrupt with monitor mode.
BDCOP — Break Disable COP Bit
15.2.2.4 Break Status Register
The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode.
This register is only used in emulation mode.
SBSW — SIM Break Stop/Wait
15.2.2.5 Break Flag Control Register
The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU
is in a break state.
Freescale Semiconductor
This read/write bit disables the COP during a break interrupt. Reset clears the BDCOP bit.
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
1 = COP disabled during break interrupt
0 = COP enabled during break interrupt.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
Address: $FE02
Address: $FE00
Address: $FE03
Reset:
Reset:
Read:
Read:
Reset:
Write:
Write:
Read:
Write:
BCFE
Bit 7
Bit 7
Bit 7
R
R
0
0
R
0
Figure 15-8. Break Flag Control Register (BFCR)
Figure 15-6. Break Auxiliary Register (BRKAR)
Figure 15-7. Break Status Register (BSR)
= Unimplemented
= Reserved
= Reserved
MC68HLC908QY/QT Family Data Sheet, Rev. 3
R
6
0
0
6
R
6
R
5
0
0
5
R
5
R
4
0
0
4
R
4
1. Writing a 0 clears SBSW.
R
3
0
0
3
R
3
R
2
0
0
2
R
2
Note
SBSW
1
0
0
1
0
R
1
(1)
BDCOP
Break Module (BRK)
Bit 0
Bit 0
Bit 0
R
0
R
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