MCHLC908QY2CPE Freescale Semiconductor, MCHLC908QY2CPE Datasheet - Page 55

• Manufacturer Part Number: MCHLC908QY2CPE
• Description: IC MCU 1.5K FLASH 8MHZ 16-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHLC908QY2CPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 2MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

LVIPWRD — LVI Power Disable Bit
LVDLVR — Low Voltage Detect or Low Voltage Reset Mode Bit
SSREC — Short Stop Recovery Bit
STOP — STOP Instruction Enable Bit
COPD — COP Disable Bit
Freescale Semiconductor
LVIPWRD disables the LVI module.
LVDLVR selects the trip voltage of the LVI module. LVD trip voltage can be used as a low voltage
warning, while LVR will commonly be used as a reset condition. Unlike other CONFIG bits, LVDLVR
can be written multiple times after reset.
SSREC enables the CPU to exit stop mode with a delay of 32 BUSCLKX4 cycles instead of a 4096
BUSCLKX4 cycle delay.
The system stabilization time for power-on reset and long stop recovery (both 4096 BUSCLKX4
cycles) gives a delay longer than the LVI enable time for these startup scenarios. There is no period
where the MCU is not protected from a low-power condition. However, when using the short stop
recovery configuration option, the 32 BUSCLKX4 delay must be greater than the LVI’s turn on time to
avoid a period in startup where the LVI is not protecting the MCU.
STOP enables the STOP instruction.
COPD disables the COP module.
1 = LVI module power disabled
0 = LVI module power enabled
1 = LVI trip voltage level set to LVD trip voltage
0 = LVI trip voltage level set to LVR trip voltage
1 = Stop mode recovery after 32 BUSCLKX4 cycles
0 = Stop mode recovery after 4096 BUSCLKX4 cycles
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
1 = COP module disabled
0 = COP module enabled
The LVDLVR bit is cleared by a power-on reset (POR) only. Other resets
will leave this bit unaffected.
Exiting stop mode by an LVI reset will result in the long stop recovery.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
NOTE
NOTE
Functional Description
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