M30263F6AFP#U7 Renesas Electronics America, M30263F6AFP#U7 Datasheet - Page 339
![IC M16C/26A MCU FLASH 42SSOP](/photos/28/61/286144/42-ssop_sml.jpg)
M30263F6AFP#U7
Manufacturer Part Number
M30263F6AFP#U7
Description
IC M16C/26A MCU FLASH 42SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheet
1.M30260F3AGPU5A.pdf
(354 pages)
Specifications of M30263F6AFP#U7
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
33
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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19.13 Flash Memory Version
e
E
1
. v
J
6
0
C
19.13.1 Functions to Inhibit Rewriting Flash Memory
19.13.2 Stop mode
19.13.3 Wait mode
19.13.4 Low power dissipation mode, on-chip oscillator low power dissipation mode
19.13.5 Writing command and data
19.13.6 Program Command
19.13.7 Operation speed
19.13.8 Instructions prohibited in EW0 Mode
2
9
0 .
B
2 /
ID codes are stored in addresses 0FFFDF
and 0FFFFB
standard serial I/O mode.
The ROMCP register is mapped in address 0FFFFF
memory cannot be read or written in parallel I/O mode.
In the flash memory version of microcomputer, these addresses are allocated to the vector addresses (H)
of fixed vectors.The b3 to b0 in address 0FFFFF
When the microcomputer enters stop mode, execute the instruction which sets the CM10 bit to “1”(stop
mode) after setting the FMR01 bit to “0”(CPU rewrite mode disabled) and disabling the DMA transfer.
When the microcomputer enters wait mode, excute the WAIT instruction after setting the FMR01 bit to
“0”(CPU rewrite mode disabled).
If the CM05 bit is set to “1” (main clock stop), the following commands must not be executed.
• Program
• Block erase
Write the command code and data at even addresses.
Write ‘xx40
auto program operation (data program and verify) will start. Make sure the address value specified in the
first bus cycle is the same even address as the write address specified in the second bus cycle.
When CPU clock source is main clock, before entering CPU rewrite mode (EW0 or EW1 mode), select 10
MHz or less for BCLK using the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1
register. Also, when CPU clock is f
(EW0 or EW1 mode), set the ROCR3 to ROCR2 bits in the ROCR register to “divied by 4” or “divide by 8”.
On both cases, set the PM17 bit in the PM1 register to “1” (with wait state).
The following instructions cannot be used in EW0 mode because the flash memory’s internal data is
referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
0
0
6
2
A
0
F
2
e
G
0 -
b
o r
1 .
2
0
u
, 5
0
p
2
16
(
0
M
16
0
’ in the first bus cycle and write data to the write address in the second bus cycle, and an
7
1
. If wrong data is written to these addresses, the flash memory cannot be read or written in
6
C
page 320
2 /
6
, A
M
1
f o
6
C
3
2
2 /
9
6
, B
3
(ROC) on-chip oscillator clock, before entering CPU rewrite mode
M
1
6
C
2 /
16
6
, 0FFFE3
) T
16
are reserved bits. Set these bits to “1111
16
. If wrong data is written to this address, the flash
16
, 0FFFEB
16
, 0FFFEF
16
, 0FFFF3
16
19. Usage Notes
, 0FFFF7
2
”.
16
,
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