M30263F6AFP#U7 Renesas Electronics America, M30263F6AFP#U7 Datasheet - Page 55
![IC M16C/26A MCU FLASH 42SSOP](/photos/28/61/286144/42-ssop_sml.jpg)
M30263F6AFP#U7
Manufacturer Part Number
M30263F6AFP#U7
Description
IC M16C/26A MCU FLASH 42SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheet
1.M30260F3AGPU5A.pdf
(354 pages)
Specifications of M30263F6AFP#U7
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
33
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M
R
R
e
E
1
. v
Figure 6.2 PM2 Register
J
6
0
C
2
9
0 .
2 /
B
0
0
6
Processeor Mode Register 2
2
b7
NOTES:
A
0
F
2
e
G
1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable).
2. The PM20 bit become effective when PLC07 bit in the PLC0 register is set to "1" (PLL on). Change the PM20 bit
3. Once this bit is set to “1”, it cannot be set to “0” by program.
4. Writing to the following bits has no effect when the PM21 bit is set to “1”:
5. Setting the PM22 bit to “1” results in the following conditions:
6. For NMI function, the PM24 bit must be set to “1”(NMI function). Once this bit is set to “1”, it cannot be cleared to
7. SD input is valid regardless of the PM24 setting.
b6
0 -
b
o r
1 .
when the PLC07 bit is set to "0" (PLL off). Set the PM20 bit to "0" (2 waits) when PLL clock > 16 MHz.
“0” by program.
2
- The on-chip oscillator continues oscillating even if the CM21 bit in the CM2 register is set to "0" (main clock or
- The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count
- The CM10 bit in the CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode
- The watchdog timer does not stop in wait mode.
When the PM21 bit is set to "1", do not execute the WAIT instruction.
b5
0
u
, 5
PLL clock) (system clock of count source selected by the CM21 bit is valid)
source.
entered)
0
p
CM02 bit in the CM0 register
CM05 bit in the CM0 register (main clock is not halted)
CM07 bit in the CM0 register (CPU clock source does not change)
CM10 bit in the CM1 register (stop mode is not entered)
CM11 bit in the CM1 register (CPU clock source does not change)
CM20 bit in the CM2 register (oscillation stop, re-oscillation detection function settings do not change)
All bits in the PLC0 register (PLL frequency synthesizer setting do not change)
2
b4
(
0
M
0
0
b3
7
1
6
C
b2
2 /
page 36
b1
6
, A
b0
M
1
Bit Symbol
f o
6
(b7-b5)
PM20
PM21
PM22
PM24
C
3
(b3)
Symbol
PM2
2
2 /
9
6
, B
(1)
M
Specifying wait when
accessing SFR during PLL
operation
System clock protective bit
WDT count source
protective bit
Reserved bit
P85/NMI configuration bit
Nothing is assigned. When write, set to“0”.
When read,its content is indeterminate
1
6
C
2 /
6
(2)
Bit Name
) T
(3,5)
Address
001E
16
(6,7)
(3,4)
After Reset
XXX00000
0: 2 wait
1: 1 wait
0: Clock is protected by PRCR
1: Clock modification disabled
0: CPU clock is used for the
1: On-chip oscillator clock is used
Set to “0”
0: P8
1: NMI function
register
watchdog timer count source
for the watchdog timer count
source
5
function (NMI disable)
2
Function
6. Processor Mode
RW
RW
RW
RW
RW
RW
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