M30263F6AFP#U7 Renesas Electronics America, M30263F6AFP#U7 Datasheet - Page 51
![IC M16C/26A MCU FLASH 42SSOP](/photos/28/61/286144/42-ssop_sml.jpg)
M30263F6AFP#U7
Manufacturer Part Number
M30263F6AFP#U7
Description
IC M16C/26A MCU FLASH 42SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheet
1.M30260F3AGPU5A.pdf
(354 pages)
Specifications of M30263F6AFP#U7
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
33
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Table 5.5.1.1 Voltage Down Detection Interrupt Request Generation Conditions
Table 5.5.1.2 Sampling Periods
NOTES:
0
C
Operation Mode
2
5.5.1 Voltage Down Detection Interrupt
9
CPU
Clock
(MHz)
Wait Mode
Stop Mode
0 .
2 /
B
1. The status except the wait mode and stop mode is handled as the normal mode.(Refer to 7. Clock generating circuit)
2. Refer to 5.5.2 Limitations on stop mode, 5.5.3 Limitations on wait mode.
3. An interrupt request for voltage reduction is generated a sampling time after the value of the VC13 bit has changed.
16
Operation
0
0
6
Mode
See the Figure 5.5.1.2 Voltage Down Detection Interrupt Generation Circuit Operation Example for details.
Normal
2
A
If the D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled), the voltage
down detection interrupt request is generated when the voltage applied to the VCC pin crosses the
Vdet4 voltage level. The voltage down detection interrupt shares the same interrupt vector with the
watchdog timer interrupt and oscillation stop, re-oscillation detection interrupt.
Set the D41 bit in the D4INT register to “1” (enabled) to use the voltage down detection interrupt to exit
stop mode.
The D42 bit in the D4INT register is set to “1” as soon as the voltage applied to the VCC pin reaches
Vdet4 due to the voltage rise and voltage drop. When the D42 bit changes “0” to “1”, the voltage down
detection interrupt request is generated. Set the D42 bit to “0” by program. However, when the D41
bit is set to “1” and the microcomputer is in stop mode, the voltage down detection interrupt request is
generated regardless of the D42 bit state if the voltage applied to the VCC pin is detected to be above
Vdet4. The microcomputer then exits stop mode.
Table 5.5.1.1 shows how the voltage down detection interrupt request is generated.
The DF1 to DF0 bits in the D4INT register determine the sampling period that detects the voltage
applied to the VCC pin reaches Vdet4. Table 5.5.1.2 shows the sampling periods.
0
F
2
e
G
0 -
b
(1)
o r
1 .
2
(CPU clock divided by 8)
(2)
(2)
0
u
, 5
0
p
2
(
DF1 to DF0=00
0
M
0
1
7
VC27 Bit
6
3.0
C
1
2 /
page 32
6
, A
M
1
f o
6
D40 Bit
C
3
2
2 /
1
(CPU clock divided by 16)
9
6
, B
DF1 to DF0=01
M
1
6
6.0
D41 Bit
C
Sampling Period ( s)
2 /
1
6
) T
D42 Bit
0 to 1
0 to 1
(CPU clock divided by 32)
DF1 to DF0=10
12.0
CM02 Bit
0
1
0
(CPU clock divided by 64)
VC13 Bit
– : “0”or “1”
0 to 1
1 to 0
0 to 1
1 to 0
0 to 1
0 to 1
DF1 to DF0=11
(3)
(3)
(3)
(3)
24.0
5. Reset
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