SAF-TC1130-L150EB BB Infineon Technologies, SAF-TC1130-L150EB BB Datasheet - Page 22

• Manufacturer Part Number: SAF-TC1130-L150EB BB
• Description: IC MCU 32BIT TRICOR 16KB LBGA208
• Manufacturer: Infineon Technologies
• Series: TC11xxr

Specifications of SAF-TC1130-L150EB BB

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Type: ROMless
• Ram Size: 144K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LSBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: FT1130L150EBBBNP; SAFTC1130L150EBBB; SP000099808

Table 2-1
Symbol
D-
CS0
CS1
CS2
CS3
CSCOMB N3
SDCLKI
SDCLKO H1
RAS
CAS
CKE
BFCLKI
BFCLKO
RD
RD/WR
WAIT
ALE
MR/W
BAA
ADV
Data Sheet
Pin
T15
D9
D8
C9
B8
J1
D6
D5
L4
D1
E1
P2
T3
B9
R3
P3
A11
B11
Pin Definitions and Functions (cont’d)
In
Out
I/O
O
O
O
O
O
I
O
O
O
O
I
O
O
O
I
O
O
O
O
PU/
PD
⎯
PUC
PUC
PUC
PUC
PUC EBU Chip Select Output for combination function
⎯
⎯
PUC EBU SDRAM Row Address Strobe Output
PUC EBU SDRAM Column Address Strobe Output
PUC EBU SDRAM Clock Enable Output
⎯
⎯
PUC EBU Read Control Line
PUC EBU Write Control Line
PUC EBU Wait Control Line
PDC EBU Address Latch Enable Output
PUC EBU Motorola-style Read/Write Output
PUC EBU Burst Address Advance Output
PUC EBU Burst Flash Address Valid Output
1)
Functions
USB D- Data Line
EBU Chip Select Output Line 0
EBU Chip Select Output Line 1
EBU Chip Select Output Line 2
EBU Chip Select Output Line 3
Each corresponds to a programmable region. Only
one can be active at one time.
(Overlay Memory and Global)
SDRAM Clock Input (Clock Feedback)
SDRAM Clock Output
Accesses to SDRAM devices are synchronized to this
clock.
Burst Flash Clock Input (Clock Feedback)
Burst Flash Clock Output
Accesses to Burst Flash devices are synchronized to
this clock.
Output in master mode
Input in slave mode
Output in master mode
Input in slave mode
For advancing address in a Burst Flash access
16
General Device Information
V1.1, 2008-12
TC1130