SAF-TC1130-L150EB BB Infineon Technologies, SAF-TC1130-L150EB BB Datasheet - Page 36

• Manufacturer Part Number: SAF-TC1130-L150EB BB
• Description: IC MCU 32BIT TRICOR 16KB LBGA208
• Manufacturer: Infineon Technologies
• Series: TC11xxr

Specifications of SAF-TC1130-L150EB BB

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Type: ROMless
• Ram Size: 144K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LSBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: FT1130L150EBBBNP; SAFTC1130L150EBBB; SP000099808

Features:
The FPI Bus is designed with the requirements of high-performance systems in mind.
The features are:
• Core independent
• Multimaster capability (up to 16 masters)
• Demultiplexed operation
• Clock synchronous
• Peak transfer rate of up to 800 Mbytes/sec (@ 100 MHz bus clock)
• Address and data bus scalable (address bus up to 32 bits, data bus up to 64 bits)
• 8-/16-/32- and 64-bit data transfers
• Broad range of transfer types from single to multiple data transfers
• Split transaction support for agents with long response time
• Burst transfer capability
• EMI and power consumption minimized
3.4.3
The LMB-to-FPI Interface (LFI) block provides the circuitry to interface (bridge) the FPI
bus and the Local Memory Bus (LMB).
LFI Features:
• Full support for bus transactions found within current TriCore™ 1.3 based systems:
• Address decoding and translation as required by TriCore™ 1.3 implementation
• FPI master interface supports full pipelining on FPI bus
• LMB master interface supports pipelining on LMB within the scope of the LMB
• FPI master interface can act as default master on FPI bus
• Programmable support for split LMB to FPI read transactions
• Retry generation on both FPI and LMB buses
• Full support for abort, retry, error and FPI timeout conditions
• Flexible LMB/FPI clock ratio support including dynamic clock switching support
• LFI core clock may be shut down when no transactions are being issued to LFI from
Data Sheet
specification
either bus and the LFI has no transactions in progress, thus saving power.
– Single 8/16/32-bit Write/Read transfers from FPI to LMB
– Single 8/16/32/64-bit Write/Read transfers from LMB to FPI
– Read-Modify-Write transfers of 8/16/32-bit in both directions
– Burst transactions of 2, 4 or 8 data beats from the FPI to the LMB
– Burst transactions of 2 or 4 data beats from the LMB to the FPI
LFI
30
Functional Description
V1.1, 2008-12
TC1130