SAF-TC1130-L150EB BB Infineon Technologies, SAF-TC1130-L150EB BB Datasheet - Page 66

• Manufacturer Part Number: SAF-TC1130-L150EB BB
• Description: IC MCU 32BIT TRICOR 16KB LBGA208
• Manufacturer: Infineon Technologies
• Series: TC11xxr

Specifications of SAF-TC1130-L150EB BB

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Type: ROMless
• Ram Size: 144K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LSBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: FT1130L150EBBBNP; SAFTC1130L150EBBB; SP000099808

3.19
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failure. The WDT helps to abort an accidental
malfunction of the TC1130 in a user-specified time period. When enabled, the WDT will
cause the TC1130 system to be reset if the WDT is not serviced within a
user-programmable time period. The CPU must service the WDT within this time interval
to prevent the WDT from causing a TC1130 system reset. Hence, routine service of the
WDT confirms that the system is functioning properly.
In addition to this standard “Watchdog” function, the WDT incorporates the ENDINIT
feature and monitors its modifications. A system-wide line is connected to the ENDINIT
bit implemented in a WDT control register, serving as an additional write-protection for
critical registers (besides supervisor mode protection). Registers protected via this line
can be modified only when supervisor mode is active and bit ENDINIT = 0.
A further enhancement in the TC1130’s Watchdog Timer is its reset prewarning
operation. Instead of immediately resetting the device upon detection of an error, the
WDT first issues a Non-Maskable Interrupt (NMI) to the CPU before finally resetting the
device at a specified time period later. This gives the CPU a chance to save system state
to memory for later examination of the cause of the malfunction, thus providing an
important aid in debugging.
Features:
• 16-bit Watchdog counter
• Selectable input frequency:
• 16-bit user-definable reload value for normal Watchdog operation, fixed reload value
• Incorporation of the ENDINIT bit and monitoring of its modifications
• Sophisticated password access mechanism with fixed and user-definable password
• Proper access always requires two write accesses. The time between the two
• Access Error Detection: Invalid password (during first access) or invalid guard bits
• Overflow Error Detection: An overflow of the counter triggers the Watchdog reset
• Watchdog function can be disabled; access protection and ENDINIT monitor function
• Double Reset Detection: If a Watchdog induced reset occurs twice without a proper
Data Sheet
for time-out and prewarning modes
fields
accesses is monitored by the WDT.
(during second access) trigger the Watchdog reset generation.
generation.
remain enabled.
access to its control register in between, a severe system malfunction is assumed and
the TC1130 is held in reset until a power-on reset or a hardware reset occurs. This
prevents the device from being periodically reset if, for instance, connection to the
Watchdog Timer
f
SYS
/256 or
f
60
SYS
/16384
Functional Description
V1.1, 2008-12
TC1130