SAF-TC1130-L150EB BB Infineon Technologies, SAF-TC1130-L150EB BB Datasheet - Page 44

• Manufacturer Part Number: SAF-TC1130-L150EB BB
• Description: IC MCU 32BIT TRICOR 16KB LBGA208
• Manufacturer: Infineon Technologies
• Series: TC11xxr

Specifications of SAF-TC1130-L150EB BB

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Type: ROMless
• Ram Size: 144K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LSBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: FT1130L150EBBBNP; SAFTC1130L150EBBB; SP000099808

TC1130
Functional Description
3.9
Asynchronous/Synchronous Serial Interface (ASC)
Figure 3-5
shows a global view of the functional blocks of three Asynchronous/
Synchronous Serial interfaces (ASC0, ASC1 and ASC2).
Each ASC module (ASC0/ASC1/ASC2) communicates with the external world via one
pair of I/O lines. The RXD line is the receive data input signal (in synchronous mode also
output). TXD is the transmit output signal. Clock control, address decoding, and interrupt
service request control are managed outside the ASC module kernel.
The Asynchronous/Synchronous Serial interfaces provide serial communication
between the TC1130 and other microcontrollers, microprocessors or external
peripherals.
Each ASC supports full-duplex asynchronous communication and half-duplex
synchronous communication. In synchronous mode, data is transmitted or received
synchronous to a shift clock which is generated by the ASC internally. In asynchronous
mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be
selected. Parity, framing, and overrun error detection are provided to increase the
reliability of data transfers. Transmission and reception of data is double-buffered. For
multiprocessor communication, a mechanism is included to distinguish address bytes
from data bytes. Testing is supported by a loop-back option. A 13-bit baud-rate generator
provides the ASC with a separate serial clock signal that can be accurately adjusted by
a prescaler implemented as a fractional divider.
Data Sheet
38
V1.1, 2008-12