XRT91L31IQ-F Exar Corporation, XRT91L31IQ-F Datasheet - Page 12

• Manufacturer Part Number: XRT91L31IQ-F
• Description: IC TXRX SONET/SDH 8BIT 64QFP
• Manufacturer: Exar Corporation
• Type: Transceiverr

Specifications of XRT91L31IQ-F

• Package / Case: 64-QFP
• Input: LVCMOS, LVPECL, LVTTL
• Output: LVCMOS, LVPECL, LVTTL
• Frequency - Max: 77.76MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 77.76MHz
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 155.52 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 240 mA or 270 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1361

PIN DESCRIPTION
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
PIN DESCRIPTION
POWER AND GROUND
AVDD3.3_RX
AVDD3.3_TX
FRAMEPULSE
VDD3.3
DLOSDIS
LOSEXT
N
CAP1P
CAP2P
CAP1N
CAP2N
N
AME
AME
PWR
PWR
PWR
T
SE-LVPECL
YPE
LVCMOS
LVCMOS
LVTTL,
LVTTL,
Analog
Analog
L
EVEL
18, 31, 34, 47, 61
T
YPE
O
P
-
-
I
I
38
43
IN
P
30
39
42
40
41
33
7
IN
3.3V CMOS Power Supply
VDD3.3 should be isolated from the Analog VDD power supplies.
Use a ferrite bead along with an internal power plane separation.
The VDD3.3 power supply pins should have bypass capacitors to
the nearest ground.
Analog 3.3V Transmitter Power Supply
AVDD3.3_TX should be isolated from the digital power supplies.
For best results, use a ferrite bead along with an internal power
plane separation. The AVDD3.3_TX power supply pins should
have bypass capacitors to the nearest ground.
Analog 3.3V Receiver Power Supply
AVDD3.3_RX should be isolated from the digital power supplies.
For best results, use a ferrite bead along with an internal power
plane separation. The AVDD3.3_RX power supply pins should
have bypass capacitors to the nearest ground.
Sonet Frame Alignment Pulse
This pin will generate a single pulse for an RXPCLKO clock
period upon the detection of the third frame alignment A2 byte
whenever the OOF input pin is held High. The parallel received
data output bus will then be byte aligned to this newly recov-
ered SONET/SDH frame.
CDR Non-polarized External Filter Capacitor
C1 = 0.47μF ± 10% tolerance
(Isolate from noise and place close to pin)
CDR Non-polarized External Filter Capacitor
C2 = 0.47μF ± 10% tolerance
(Isolate from noise and place close to pin)
LOS (Los of Signal) Detect Disable
Disables internal LOS monitoring and automatic muting of
RXDO[7:0] upon LOS detection. LOS is declared when a string
of 128 consecutive zeros occur on the line. LOS condition is
cleared when the 16 or more pulse transitions is detected for
128 bit period sliding window (see
"Low" = Monitor and Mute received data upon LOS declaration
"High" = Disable internal LOS monitoring
LOS or Signal Detect Input from Optical Module
Active "Low." When active, this pin can force the received data
output bus RXDO[7:0] to a logic state of ’0’ per
"Low" = Forced LOS
"High" = Normal Operation
12
D
D
ESCRIPTION
ESCRIPTION
Figure 7
.)
Figure 7
REV. 1.0.2
.