AK5388EQP AKM Semiconductor Inc, AK5388EQP Datasheet - Page 12

• Manufacturer Part Number: AK5388EQP
• Description: IC ADC AUDIO STER 24BIT 44LQFP
• Manufacturer: AKM Semiconductor Inc
• Type: ADCr

Specifications of AK5388EQP

• Resolution (bits): 24 b
• Sampling Rate (per Second): 8k ~ 216k
• Data Interface: I²S, Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 3.3V, 5V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 974-1035

Parameter
Audio Interface Timing (Master mode)
Power-Down & Reset Timing
Note 14. BICK rising edge must not occur at the same time as LRCK edge.
Note 15. SDTO2 output is fixed to “L”.
Note 16. This value is MCLK=512fs. Duty cycle is not guaranteed when MCLK=256fs/384fs.
Note 17. The AK5388 can be reset by bringing the PDN pin = “L”.
Note 18. This cycle is the number of LRCK rising edges from the PDN pin = “H”. The value is when the AK5388 is in
MS1096-E-01
PDN Pulse Width
PDN “↑” to SDTO1/2 valid
Normal mode (TDM1=“L”, TDM0=“L”)
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO1/2
TDM256 mode (TDM1=“L”, TDM0=“H”)
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO1
TDM128 mode (TDM1=“H”, TDM0=“H”)
TDM128 mode (TDM1=“H”, TDM0=“H”)
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO1
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO1
(8KHz ≤ fs < 108KHz)
(108KHz < fs ≤ 216KHz)
master mode. In case of in slave mode, the value will be 1LRCK clock cycle (1/fs) longer.
(Note
(Note
(Note
(Note
(Note
15)
15)
16)
17)
18)
Symbol
tMBLR
tMBLR
tMBLR
tMBLR
dBCK
dBCK
dBCK
dBCK
fBCK
fBCK
fBCK
fBCK
tPDV
tBSD
tBSD
tBSD
tBSD
tPD
- 12 -
min
−20
−20
−12
−20
−12
−20
−10
150
−6
256fs
128fs
128fs
64fs
516
typ
50
50
50
50
max
20
20
12
20
12
20
10
6
[AK5388]
Units
2009/08
1/fs
Hz
Hz
Hz
Hz
%
ns
ns
%
ns
ns
%
ns
ns
%
ns
ns
ns