AK5388EQP AKM Semiconductor Inc, AK5388EQP Datasheet - Page 21

• Manufacturer Part Number: AK5388EQP
• Description: IC ADC AUDIO STER 24BIT 44LQFP
• Manufacturer: AKM Semiconductor Inc
• Type: ADCr

Specifications of AK5388EQP

• Resolution (bits): 24 b
• Sampling Rate (per Second): 8k ~ 216k
• Data Interface: I²S, Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 3.3V, 5V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 974-1035

■
The ADC has a digital high pass filter for DC offset cancellation. The HPF is controlled by the HPFE pin. If the HPF
setting (ON/OFF) is changed during operation, a click noise occurs due to the change in DC offset. The HPF setting
should only be changed when the PDN pin = “L”.
■
The AK5388 has an overflow detect function for the analog input. The OVF pin goes to “H” if either channel overflows
(more than −0.3dBFS). OVF output for overflowed analog input has the same group delay as the ADC
(GD=13/fs=0.27ms@fs=48kHz). OVF is “L” for 516/fs (=10.75ms@fs=48kHz) after the PDN pin = “↑”, and then
overflow detection is enabled.
■
The AK5388 is placed in the power-down mode by bringing PDN pin “L” and the digital filter is also reset at the same
time. This reset should always be done after power-up. In the power-down mode, the VCOM is AGND level. An analog
initialization cycle starts after exiting the power-down mode. The output data SDTO is valid after 516 cycles of LRCK
clock in master mode (517 cycles in slave mode). During initialization, the ADC digital data outputs of both channels are
forced to “0”. The ADC outputs settle to data correspondent to the input signals after the end of initialization (Settling
takes approximately the group delay time).
The AK5388 should be reset once by bringing the PDN pin “L” after power-up. The internal timing starts clocking by the
rising edge (falling edge at Mode 1) of LRCK after exiting from reset and power down state by MCLK.
Notes:
MS1096-E-01
(1) 517/fs in slave mode and 516/fs in master mode.
(2) Digital output corresponding to analog input has group delay (GD).
(3) A/D output is “0” data in power-down state.
(4) When the external clocks (MCLK, SCLK, LRCK) are stopped, the AK5388 should be in the power-down state.
Digital High Pass Filter (HPF)
Overflow Detection
Power Down and Reset
Internal
A/D In
A/D Out
Clock In
MCLK,LRCK,SCLK
PDN
(Analog)
(Digital)
State
Normal Operation
Idle Noise
Figure 16. Power-down/up sequence example
GD
(2)
(4)
Power-down
“0”data
- 21 -
(3)
Initialize
“0”data
(1)
Idle Noise
Normal Operation
GD
[AK5388]
2009/08