AK5388EQP AKM Semiconductor Inc, AK5388EQP Datasheet - Page 18

no-image

AK5388EQP

Manufacturer Part Number
AK5388EQP
Description
IC ADC AUDIO STER 24BIT 44LQFP
Manufacturer
AKM Semiconductor Inc
Type
ADCr
Datasheets

Specifications of AK5388EQP

Resolution (bits)
24 b
Sampling Rate (per Second)
8k ~ 216k
Data Interface
I²S, Serial
Voltage Supply Source
Analog and Digital
Voltage - Supply
3.3V, 5V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
974-1035

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AK5388EQP
Manufacturer:
Maxim
Quantity:
32
Part Number:
AK5388EQP
Manufacturer:
AKM Semiconductor Inc
Quantity:
10 000
When changing MCLK frequency in master/slave mode, the AK5388 should reset by PDN pin = “L”. (ex.
12.288MHz(@fs=48kHz) at CKS1 pin = CKS0 pin = “L”.
12 different audio data interface formats can be selected using the TDM1-0, M/S and DIF pins as shown in
audio data format can be selected by the DIF pin. In all formats the serial data is MSB-first, 2's compliment format. The
SDTO1/2 is clocked out on the falling edge of BICK.
In normal mode, Mode 0-1 are the slave mode, and BICK is available up to 128fs at fs=48kHz. BICK outputs 64fs clock
in Mode 2-3.
In TDM256 mode, all of the ADC’s serial data (four channels) is output from the SDTO1 pins. The SDTO2 output is
fixed to “L”. BICK should be fixed to 256fs. In slave mode, “H” time and “L” time of LRCK should be at least 1/256fs. In
master mode, “H” time (“L” time at I
In TDM128 mode, all of the ADC’s serial data (four channels) is output from the SDTO1 pin. The SDTO2 output is fixed
to “L”. BICK should be fixed to 128fs. In the slave mode, “H” time and “L” time of LRCK should be at least 1/128fs. In
master mode, “H” time (“L” time at I
MS1096-E-01
Audio Interface Format
CKS2 pin
H
H
H
H
L
L
L
L
CKS1 pin
H
H
H
H
L
L
L
L
2
2
S mode) of LRCK is 1/4fs (typ). TDM128 mode supports up to 192kHz sampling.
S mode) of LRCK is 1/8fs (typ). TDM256 mode only supports 48kHz sampling.
CKS0 pin
H
H
H
H
L
L
L
L
Table 4. MCLK Frequency
M/S Pin
- 18 -
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
128fs (108KHz < fs ≤ 216KHz)
192fs (108KHz < fs ≤ 216KHz)
256fs (54KHz < fs ≤ 108KHz)
384fs (54KHz < fs ≤ 108KHz)
Auto (8KHz ≤ fs ≤ 216KHz)
256fs (8KHz ≤ fs ≤ 54KHz)
384fs (8KHz ≤ fs ≤ 54KHz)
512fs (8KHz < fs ≤ 54KHz)
768fs (8KHz ≤ fs ≤ 54KHz)
Double Speed Mode
Normal Speed Mode
Double Speed Mode
Double Speed Mode
Normal Speed Mode
Normal Speed Mode
Normal Speed Mode
Quad Speed Mode
MCLK Frequency
Table
[AK5388]
2009/08
5. The

Related parts for AK5388EQP