ATMEGA8515L-8JU Atmel, ATMEGA8515L-8JU Datasheet - Page 117

• Manufacturer Part Number: ATMEGA8515L-8JU
• Description: MCU AVR 8K ISP FLASH MEM 44-PLCC
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8515L-8JU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LCC (J-Lead)
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 512Byte
• # I/os (max): 35
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Timer/Counter Timing
Diagrams
2512K–AVR–01/10
The Timer/Counter is a synchronous design and the timer clock (clk
shown as a clock enable signal in the following figures. The figures include information
on when Interrupt Flags are set, and when the OCR1x Register is updated with the
OCR1x buffer value (only for modes utilizing double buffering). Figure 56 shows a timing
diagram for the setting of OCF1x.
Figure 56. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
Figure 57 shows the same timing data, but with the prescaler enabled.
Figure 57. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f
Figure 58 shows the count sequence close to TOP in various modes. When using phase
and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The
timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by
BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag
at BOTTOM.
TCNTn
OCRnx
OCFnx
OCRnx
(clk
TCNTn
OCFnx
(clk
clk
clk
clk
clk
I/O
I/O
I/O
Tn
I/O
Tn
/1)
/8)
OCRnx - 1
OCRnx - 1
OCRnx
OCRnx
OCRnx Value
OCRnx Value
OCRnx + 1
OCRnx + 1
ATmega8515(L)
T1
) is therefore
OCRnx + 2
OCRnx + 2
clk_I/O
117
/8)