ATMEGA8515L-8JU Atmel, ATMEGA8515L-8JU Datasheet - Page 90

• Manufacturer Part Number: ATMEGA8515L-8JU
• Description: MCU AVR 8K ISP FLASH MEM 44-PLCC
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8515L-8JU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LCC (J-Lead)
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 512Byte
• # I/os (max): 35
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

90
ATmega8515(L)
Figure 42. Timer/Counter Timing Diagram, with Prescaler (f
Figure 43 shows the setting of OCF0 in all modes except CTC mode.
Figure 43. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (f
Figure 44 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode.
Figure 44. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with
Prescaler (f
TCNTn
TCNTn
TCNTn
(clk
(clk
(clk
OCRn
(CTC)
OCRn
OCFn
TOVn
OCFn
clk
clk
clk
clk
clk
clk
I/O
I/O
I/O
I/O
I/O
I/O
Tn
Tn
Tn
/8)
/8)
/8)
clk_I/O
/8)
OCRn - 1
MAX - 1
TOP - 1
OCRn
MAX
TOP
OCRn Value
TOP
OCRn + 1
BOTTOM
BOTTOM
clk_I/O
/8)
2512K–AVR–01/10
BOTTOM + 1
BOTTOM + 1
OCRn + 2
clk_I/O
/8)