AT91SAM7S128C-AU Atmel, AT91SAM7S128C-AU Datasheet - Page 130
![IC ARM7 MCU 32BIT 128K 64LQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
AT91SAM7S128C-AU
Manufacturer Part Number
AT91SAM7S128C-AU
Description
IC ARM7 MCU 32BIT 128K 64LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91SAM7S16-MU.pdf
(51 pages)
2.AT91SAM7S16-MU.pdf
(779 pages)
3.AT91SAM7S256C-MU.pdf
(2 pages)
Specifications of AT91SAM7S128C-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
AT91SAM7S128-AU-001
AT91SAM7S128AU001
AT91SAM7S128AU001
AT91SAM7S128AU001
AT91SAM7S128AU001
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7S128C-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 130 of 779
- Download datasheet (11Mb)
20.2.5
20.2.5.1
130
AT91SAM7S Series Preliminary
Device Operations
Flash Read Command
Several commands on the Flash memory are available. These commands are summarized in
Table 20-3 on page
face running several read/write handshaking sequences.
When a new command is executed, the previous one is automatically achieved. Thus, chaining
a read command after a write automatically flushes the load buffer in the Flash.
In the following tables, 21-6 through 21-18
This command is used to read the contents of the Flash memory. The read command can start
at any valid address in the memory plane and is optimized for consecutive reads. Read hand-
shaking can be chained; an internal address buffer is automatically increased.
Table 20-6.
Table 20-7.
Step
1
2
3
4
5
...
n
n+1
n+2
n+3
...
Step
1
2
3
4
5
6
7
...
n
• DATA[15:0] pertains to AT91SAM7S512/256/128/64/321/161
• DATA[7:0] pertains to AT91SAM7S32/16
Handshake Sequence
Write handshaking
Write handshaking
Write handshaking
Read handshaking
Read handshaking
...
Write handshaking
Write handshaking
Read handshaking
Read handshaking
...
Handshake Sequence
Write handshaking
Write handshaking
Write handshaking
Write handshaking
Write handshaking
Read handshaking
Read handshaking
...
Write handshaking
Read Command
Read Command
126. Each command is driven by the programmer through the parallel inter-
MODE[3:0]
CMDE
ADDR0
ADDR1
DATA
DATA
...
ADDR0
ADDR1
DATA
DATA
...
MODE[3:0]
CMDE
ADDR0
ADDR1
ADDR2
ADDR3
DATA
DATA
...
ADDR0
DATA[15:0]
READ
Memory Address LSB
Memory Address
*Memory Address++
*Memory Address++
...
Memory Address LSB
Memory Address
*Memory Address++
*Memory Address++
...
READ
Memory Address LSB
Memory Address
Memory Address
Memory Address
*Memory Address++
*Memory Address++
...
Memory Address LSB
DATA[7:0]
6175K–ATARM–30-Aug-10
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