MC9S08DZ96MLF Freescale Semiconductor, MC9S08DZ96MLF Datasheet - Page 403
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MC9S08DZ96MLF
Manufacturer Part Number
MC9S08DZ96MLF
Description
MCU 8BIT 96K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DZ96MLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DZ96MLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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18.3.3.10 Debug Comparator B Extension Register (DBGCBX)
1
Freescale Semiconductor
end-run
Module Base + 0x0009
end-run
or non-
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
PAGSEL
RWBEN
Reset
Bit 16
Field
RWB
POR
7
6
5
0
W
R
1
RWBEN
Read/Write Comparator B Enable Bit — The RWBEN bit controls whether read or write comparison is enabled
for Comparator B. In full modes, RWAEN and RWA are used to control comparison of R/W and RWBEN is
ignored.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
Read/Write Comparator B Value Bit — The RWB bit controls whether read or write is used in compare for
Comparator B. The RWB bit is not used if RWBEN = 0. In full modes, RWAEN and RWA are used to control
comparison of R/W and RWB is ignored.
0 Write cycle will be matched
1 Read cycle will be matched
Comparator B Page Select Bit — This PAGSEL bit controls whether Comparator B will be qualified with the
internal signal (mmu_papge_sel) that indicates an extended access through the PPAGE mechanism. When
mmu_ppage_sel = 1, the 17-bit core address is a paged program access, and the 17-bit core address is made
up of PPAGE[2:0]:addr[13:0]. When mmu_papge_sel = 0, the 17-bit core address is either a 16-bit CPU address
with a leading 0 in bit 16, or a 17-bit linear address pointer value. This bit is not used in full modes where
comparator B is used to match the data value.
0 Match qualified by mmu_ppage_sel = 0 so address bits [16:0] correspond to a 17-bit CPU address with a
1 Match qualified by mmu_ppage_sel = 1 so address bits [16:0] compare to flash memory address made up of
Comparator B Extended Address Bit 16 Compare Bit — The Comparator B bit 16 compare bit controls
whether Comparator B will compare the core address bus bit 16 to a logic 1 or logic 0. This bit is not used in full
modes where comparator B is used to match the data value.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
U
0
7
leading zero at bit 16, or a 17-bit linear address pointer address
PPAGE[2:0]:addr[13:0]
Figure 18-11. Debug Comparator B Extension Register (DBGCBX)
= Unimplemented or Reserved
RWB
U
0
6
Table 18-12. DBGCBX Field Descriptions
MC9S08DZ128 Series Data Sheet, Rev. 1
PAGSEL
U
0
5
0
0
0
4
Description
0
0
0
3
Chapter 18 Debug Module (S08DBGV3) (128K)
0
0
0
2
0
0
0
1
Bit 16
U
0
0
403
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