MCF5328CVM240 Freescale Semiconductor, MCF5328CVM240 Datasheet

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... Interrupt Controllers (x2) • DMA Controller • FlexBus (External Interface) • Chip Configuration Module (CCM) • Reset Controller • General Purpose I/O interface © Freescale Semiconductor, Inc., 2008. All rights reserved. Document Number: MCF5329DS Rev. 5, 11/2008 MCF5329 MAPBGA–256 MAPBGA–196 ...

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... Timer Module Timing Specifications . . . . . . . . . 39 5.17 QSPI Electrical Specifications . . . . . . . . . . . . . . . . . . . 39 5.18 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 40 5.19 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 42 6 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.1 Package Dimensions—256 MAPBGA . . . . . . . . . . . . . 45 7.2 Package Dimensions—196 MAPBGA . . . . . . . . . . . . . 46 8 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 ® Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor ...

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... Table 1. MCF532x Family Configurations Module ColdFire Version 3 Core with EMAC (Enhanced Multiply-Accumulate Unit) Core (System) Clock Peripheral and External Bus Clock (Core clock ÷ 3) Performance (Dhrystone/2.1 MIPS) Unified Cache Static RAM (SRAM) MCF532x ColdFire Freescale Semiconductor (To/From SRAM backdoor) SDRAMC XBS ...

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... FlexBus External Interface General Purpose I/O Module (GPIO) ® JTAG - IEEE 1149.1 Test Access Port Package 2 Ordering Information Freescale Part Number MCF5327CVM240 MCF5327 RISC Microprocessor MCF5328CVM240 MCF5328 RISC Microprocessor MCF53281CVM240 MCF53281 RISC Microprocessor MCF5329CVM240 MCF5329 RISC Microprocessor MCF532x ColdFire 4 MCF5327 MCF5328 • • ...

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... EV /SDV high impedance state. There is no limit on how long after must powered up. IV should not lead the EV DD MCF532x ColdFire Freescale Semiconductor and the PLLV pins. The resistor and capacitors should be placed Ω 10 µF 0.1 µF GND Figure 2. System PLL V ...

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... Microprocessor Data Sheet, Rev SDV must power down. IV should DD DD MCF53281 MCF5327 MCF5328 MCF5329 196 256 256 MAPBGA MAPBGA MAPBGA J11 N15 N15 P14 P14 P14 L14 P16 P16 K14 N16 N16 M11 P13 P13 N11 R13 R13 Freescale Semiconductor ...

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... FB_D[31:17 — FB_D[16] BE/BWE[3:0] PBE[3:0] SD_DQM[3:0] OE PBUSCTL3 2 TA PBUSCTL2 R/W PBUSCTL1 TS PBUSCTL0 FB_CS[5:4] PCS[5:4] FB_CS[3:1] PCS[3:1] FB_CS0 — MCF532x ColdFire Freescale Semiconductor Alternate 2 Mode Selection — — I EVDD — — I EVDD FlexBus — O SDVDD — — O SDVDD 3 — O SDVDD 3 — ...

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... MCF5328 MCF5329 196 256 256 MAPBGA MAPBGA MAPBGA — J13 J13 J13 — J14 J14 — J15 J15 L13 J16 J16 M14 K14 K14 M13 K15 K15 N13 K16 K16 — — — — — — — — — Freescale Semiconductor ...

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... LCD_ACD/ PLCDCTLH0 LCD_OE LCD_CLS PLCDCTLL7 LCD_CONTRAST PLCDCTLL6 LCD_FLM/ PLCDCTLL5 LCD_VSYNC LCD_LP/ PLCDCTLL4 LCD_HSYNC LCD_LSCLK PLCDCTLL3 LCD_PS PLCDCTLL2 LCD_REV PLCDCTLL1 LCD_SPL_SPR PLCDCTLL0 MCF532x ColdFire Freescale Semiconductor Alternate 2 ULPI_DIR — I EVDD — O EVDD — — O EVDD — I EVDD — — I EVDD LCD Controller CANTX — ...

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... L15 H13 L16 L16 K13 M15 M15 J12 M16 M16 — H13 H13 — H14 H14 H14 H15 H15 J14 H16 H16 — — — — — G2 — — G1 — G2 — — G1 — — — F3 — — — — Freescale Semiconductor ...

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... DT2IN PTIMER2 DT1IN PTIMER1 DT0IN PTIMER0 7 JTAG_EN — DSCLK — PSTCLK — BKPT — DSI — DSO — DDATA[3:0] — MCF532x ColdFire Freescale Semiconductor Alternate 2 QSPI U2RTS — O EVDD PWM7 USBOTG_ O EVDD PU_EN PWM5 — O EVDD 2 I2C_SCL — O EVDD U2CTS — ...

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... E9, F9–F11, F8–F10, G11, H11, G11, H11, J5–J7, K7 J5, J6, K5, J5, J6, K5, K6, L5–L8, K6, L5–L8, M6, M7 M6, M7 G10 L14 L14 G6–G9, G7–G10, G7–G10, H7–H10, H7–H10, J7–10, J7–10, K7–K10, K7–K10, L12, L13 L12, L13 H11 K13 K13 H12 M14 M14 Freescale Semiconductor ...

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... MCF532x ColdFire Freescale Semiconductor Pin Assignments and Reset States ® Microprocessor Data Sheet, Rev ...

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... SD_DR P SD_A10 SD_CAS D22 D18 _DQS R SD_CLK SD_CLK SD_RAS D21 D17 T NC FB_CLK D23 D20 D16 Figure 4. MCF5328CVM240, MCF53281CVM240, and MCF5329CVM240 Pinout Top View (256 MAPBGA) 14 NOTE NOTE FEC_ LCD_ FEC_ LCD_ LCD_ RXD2 D15 COL CLS LSCLK FEC_ LCD_ FEC_ ...

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... The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. However, for production silicon, these specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed. MCF532x ColdFire Freescale Semiconductor ...

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... Section 5.4, “DC Electrical Specifications.” and range during instantaneous and DD > and could result in external power supply going DD load shunts current greater than maximum injection DD range during instantaneous and DD ® Microprocessor Data Sheet, Rev. 5 Unit °C ° greater than DD Freescale Semiconductor ...

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... Power Dissipation on Input and Output Pins — User Determined I/O For most applications P < P and can be ignored. An approximate relationship between P I/O INT Solving equations 1 and 2 for K gives: K MCF532x ColdFire Freescale Semiconductor Table 5. Thermal Characteristics Symbol θ Four layer board JMA (2s2p) θ Four layer board JMA (2s2p) θ ...

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... Units 2000 V Min Max Unit 1.4 1.6 V 1.4 1.6 V 3.0 3 1.70 1.95 2.25 2.75 3.0 3.6 3 – 0.3 0 0.4 — – — 0 0.3 1.35 SDV DD + 0.3 1.7 SDV DD + 0.3 2 SDV – 0.3 0. – 0.3 0 – 0.3 0.8 SS Freescale Semiconductor ...

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... Crystal Mode All other modes (External, Limp PLL Lock Time 3 8 Duty Cycle of reference 9 XTAL Current 10 Total on-chip stray capacitance on XTAL 11 Total on-chip stray capacitance on EXTAL MCF532x ColdFire Freescale Semiconductor Symbol SDV OH SDV Max APU C in Table 8. PLL Electrical Characteristics Symbol ...

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... Figure 8. ® Microprocessor Data Sheet, Rev. 5 Min. Max. Unit Value Value See crystal spec 2*C – – S_XTAL 7 C PCB_XTAL 2*C – – S_EXTAL 7 C PCB_EXTAL — sys/3 — TBD % f sys/3 0.8 2.2 %f sys/3 350 540 MHz . sys Table 9 Freescale Semiconductor ...

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... Frequency of Operation FB1 Clock Period (FB_CLK) Address, Data, and Control Output Valid (A[23:0], D[31:0], FB2 FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE) Address, Data, and Control Output Hold (A[23:0], D[31:0], FB3 FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE) MCF532x ColdFire Freescale Semiconductor 1.5V TSETUP THOLD Invalid 1.5V Valid 1. ...

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... ADDR[23:0] FB2 ADDR[31:X] DATA FB4 FB6 Figure 7. FlexBus Read Timing ® Microprocessor Data Sheet, Rev. 5 Symbol Min Max Unit t 3.5 — ns DVFBCH t 0 — ns DIFBCH t 4 — ns CVFBCH t 0 — ns CIFBCH Section 5.7.2, “DDR SDRAM AC S3 FB3 FB5 FB7 Freescale Semiconductor ...

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... Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD5 SD_CS[1:0] - Output Valid Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD6 SD_CS[1:0] - Output Hold 5 SD7 SD_SDR_DQS Output Valid SD_DQS[3:0] input setup relative to SD_CLK SD8 MCF532x ColdFire Freescale Semiconductor FB1 ADDR[23:0] FB2 ADDR[31:X] DATA FB6 FB7 Figure 8. FlexBus Write Timing Table 10 ...

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... SD11 SD12 WD1 WD2 WD3 Figure 9. SDR Write Timing ® Microprocessor Data Sheet, Rev. 5 Min Max Unit Does not apply. 0.5×SD_CLK fixed width. 0.25 × — ns SD_CLK 1.0 — ns 0.75 × SD_CLK — 0.5 1.5 — ns SD3 WD4 Freescale Semiconductor ...

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... Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, DD5 SD_CS[1:0] - Output Hold DD6 Write Command to first DQS Latching Transition Data and Data Mask Output Setup (DQ-->DQS) Relative DD7 DQS (DDR Write Mode) MCF532x ColdFire Freescale Semiconductor SD2 SD5 3/4 MCLK Reference COL tDQS SD6 Board Delay Board Delay ...

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... Symbol t DQDMI 7 t DVDQ 8 0.25 × SD_CLK t DIDQ t DQLSDCH t DQRPRE t DQRPST t DQWPRE t DQWPST ® Microprocessor Data Sheet, Rev. 5 Min Max Unit 1.0 — ns — — 0.5ns 0.5 — ns 0.9 1.1 SD_CLK 0.4 0.6 SD_CLK 0.25 SD_CLK 0.4 0.6 SD_CLK Freescale Semiconductor ...

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... SD_CLK SD_CLK SD_CSn,SD_WE, CMD SD_RAS, SD_CAS DD4 A[13:0] ROW DM3/DM2 SD_DQS3/SD_DQS2 D[31:24]/D[23:16] MCF532x ColdFire Freescale Semiconductor DD1 DD2 DD3 DD5 DD6 COL WD1 WD2 WD3 WD4 Figure 11. DDR Write Timing ® Microprocessor Data Sheet, Rev. 5 Electrical Characteristics DD7 DD8 DD7 ...

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... Table 12. GPIO Timing Symbol t CHPOV t CHPOI t PVCH t CHPI ® Microprocessor Data Sheet, Rev. 5 DD3 DD9 DQS Read Postamble WD1 WD2 WD3 WD4 DQS Read Preamble Postamble WD1 WD2 WD3 WD4 Min Max Unit — 1.5 — — ns 1.5 — ns Freescale Semiconductor ...

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... Thus, RESET must be held a minimum of 100 ns. FB_CLK R1 RESET RSTOUT Configuration Overrides*: (RCON, Override pins]) Figure 14. RESET and Configuration Override Timing Refer to the CCM chapter of the MCF5329 Reference Manual for more information. MCF532x ColdFire Freescale Semiconductor Figure 13. GPIO Timing Symbol t RVCH t ...

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... MCF532x ColdFire 30 Table 14. LCD_LSCLK Timing Parameter Minimum LCD_LSCLK Period Pixel data setup time Pixel data up time Non-display region T3 T4 Line 1 T6 XMAX (1,1) (1,2) (1,X) ® Microprocessor Data Sheet, Rev. 5 Maximum Unit 25 2000 ns 11 — — ns Display region Line Y T7 Freescale Semiconductor ...

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... LCD_LSCLK can be programmed to be deactivated during the LCD_VSYNC pulse or the LCD_OE deasserted period. In Note: XMAX is defined in number of pixels in one line. LCD_LSCLK LCD_LD D320 LCD_SPL_SPR T2 LCD_HSYNC T4 LCD_CLS LCD_PS T7 LCD_REV MCF532x ColdFire Freescale Semiconductor Minimum T5+T6+T7-1 — Figure 16, LCD_LSCLK is always active. XMAX ...

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... Table 17. Non-TFT Mode Panel Timing Minimum 2 1 — 1 Figure 18, all three signals are active high. When CSTN ® Microprocessor Data Sheet, Rev. 5 Value Unit 1 Ts HWAIT1+1 Ts HWAIT2 + 4 Ts CLS_RISE_DELAY+1 Ts CLS_HI_WIDTH+1 Ts PS_RISE_DELAY Ts REV_TOGGLE_DELAY Value Unit HWAIT2 + 2 Tpix HWIDTH + 1 Tpix 0 ≤ T3 ≤ Ts — HWAIT1 + 1 Tpix Freescale Semiconductor ...

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... SSI_MCLK cycle time S2 SSI_MCLK pulse width high / low S3 SSI_BCLK cycle time S4 SSI_BCLK pulse width S5 SSI_BCLK to SSI_FS output valid MCF532x ColdFire Freescale Semiconductor Table 18. These timings apply in synchronous mode only. TDD Figure 19. ULPI Timing Diagram Table 18. ULPI Interface Timing Symbol Min TSC, TSD — ...

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... Description Symbol . SYS Table 20. SSI Timing – Slave Modes Description Symbol t BCLK ® Microprocessor Data Sheet, Rev. 5 Min Max Units -2 — ns — — — — Min Max Units 8 × t — ns SYS 45% 55% t BCLK 10 — — ns — — — — ns Freescale Semiconductor ...

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... C input timing parameters shown in 2 Table 21 Input Timing Specifications between SCL and SDA Num I1 Start condition hold time I2 Clock low period I3 I2C_SCL/I2C_SDA rise time (V I4 Data hold time MCF532x ColdFire Freescale Semiconductor S10 Figure 20. SSI Timing – Master Modes S11 S12 ...

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... Microprocessor Data Sheet, Rev. 5 Min Max Units — — t cyc 0 — — t cyc 2 — t cyc 22. Min Max Units 6 — t cyc 10 — t cyc — — µs 7 — t cyc — — t cyc 2 — t cyc 20 — t cyc 10 — t cyc 2 Table 22. The I C interface Freescale Semiconductor ...

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... FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER invalid M6 FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid M7 FEC_TXCLK pulse width high M8 FEC_TXCLK pulse width low Figure 24 shows MII transmit signal timings listed in MCF532x ColdFire Freescale Semiconductor Table 23. MII Receive Signal Timing Table 23 Table 24. MII Transmit Signal Timing Table 24. ® ...

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... M13 FEC_MDIO (input) to FEC_MDC rising edge hold M14 FEC_MDC pulse width high M15 FEC_MDC pulse width low MCF532x ColdFire Min 1.5 M9 Characteristic ® Microprocessor Data Sheet, Rev. 5 Max Unit — FEC_TXCLK period Min Max Unit 0 — ns — — — ns 40% 60% FEC_MDC period 40% 60% FEC_MDC period Freescale Semiconductor ...

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... QSPI_CS[3:0] to QSPI_CLK QS2 QSPI_CLK high to QSPI_DOUT valid. QS3 QSPI_CLK high to QSPI_DOUT invalid. (Output hold) QS4 QSPI_DIN to QSPI_CLK (Input setup) QS5 QSPI_DIN to QSPI_CLK (Input hold) MCF532x ColdFire Freescale Semiconductor M14 M15 M10 M11 M12 M13 Characteristic Characteristic ® Microprocessor Data Sheet, Rev. 5 ...

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... Figure 27. QSPI Timing 1 Symbol f JCYC t JCYC t JCW t JCRF t BSDST t BSDHT t BSDV t BSDZ t TAPBST t TAPBHT t TDODV t TDODZ t TRSTAT t TRSTST ® Microprocessor Data Sheet, Rev. 5 QS5 Min Max Unit DC 1/4 f sys/3 4 — t CYC 26 — — — — — 100 — — ns Freescale Semiconductor ...

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... Data Inputs Data Outputs Data Outputs Data Outputs Figure 29. Boundary Scan (JTAG) Timing TCLK V IL TDI TMS TDO TDO TDO TCLK TRST MCF532x ColdFire Freescale Semiconductor Figure 28. Test Clock Input Timing J5 Input Data Valid J7 Output Data Valid J8 J7 Output Data Valid V ...

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... D2 D1 Figure 32. Real-Time Trace AC Timing D5 Current D4 Past Figure 33. BDM Serial Port AC Timing ® Microprocessor Data Sheet, Rev. 5 32. Max Units 1/f SYS SYS 3.0 ns — ns — PSTCLK — PSTCLK — PSTCLK — PSTCLK Next Current Table 31 shows the typical Freescale Semiconductor ...

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... See the description of the low-power control register (LCPR) in the MCF532x Reference Manual for more information on stop modes 0–3. 450 400 350 300 250 200 150 100 Figure 34. Current Consumption in Low-Power Modes MCF532x ColdFire Freescale Semiconductor 58 MHz 64 MHz 72 MHz (Typ) (Typ) (Typ) 3.9 3.92 4.0 1.04 1.04 1 ...

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... V SDV and 1 120 160 Core Frequency (MHz) ® Microprocessor Data Sheet, Rev Unit mA power DD 200 240 Freescale Semiconductor ...

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... The mechanical drawings are the latest revisions at the time of publication of this document. The most up-to-date mechanical drawings can be found at the product summary page located at http://www.freescale.com/coldfire. 7.1 Package Dimensions—256 MAPBGA Figure 36 shows MCF5328CVM240, MCF53281CVM240, and MCF5329CVM240 package dimensions Laser mark for pin A1 identification in ...

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... Parallelism measurement shall exclude any effect of mark on top surface of package. Millimeters Min Max DIM A 1.32 1.75 A1 0.27 0.47 A2 1.18 REF b 0.35 0.65 D 15.00 BSC E 15.00 BSC e 1.00 BSC S 0.50 BSC Detail K ° Rotated 90 Clockwise Freescale Semiconductor ...

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... Corrected MCF53281 in features list table. This device contains CAN, but does not feature the cryptography accelerators. • In pin-multiplexing table, moved MCF53281 label from the MCF5328 column to the MCF5329 column, because this device contains CAN output signals. MCF532x ColdFire Freescale Semiconductor Substantive Changes Section 7, “Package Information.” Figure 5 Table 5 ...

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... Minimum frequency of operation from TBD to 60MHz • Maximum clock period from TBD to 16.67 ns MCF532x ColdFire 48 Substantive Changes Table 30 from 1 sys sys Figure 7 Table 2. Table 10 and Table 11: ® Microprocessor Data Sheet, Rev. 5 Date of Release 4/2008 for min and and 11/2008 Freescale Semiconductor ...

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... MCF532x ColdFire Freescale Semiconductor ® Microprocessor Data Sheet, Rev. 5 Revision History 49 ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...